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awilliammcb30
awilliam
authored and
mcb30
committedDec 16, 2010
[igbvf] Add igbvf driver
Driver for Intel 82576 based virtual functions, based on Intel source code available at: http://sourceforge.net/projects/e1000 (igbvf-1.0.7) Based on initial port from Eric Keller <ekeller@princeton.edu>. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
·
v1.21.1v1.20.1
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‎src/Makefile

+1
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@@ -64,6 +64,7 @@ SRCDIRS += drivers/net
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SRCDIRS += drivers/net/e1000
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SRCDIRS += drivers/net/e1000e
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SRCDIRS += drivers/net/igb
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SRCDIRS += drivers/net/igbvf
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SRCDIRS += drivers/net/phantom
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SRCDIRS += drivers/net/rtl818x
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SRCDIRS += drivers/net/ath5k

‎src/drivers/net/igbvf/igbvf.h

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@@ -0,0 +1,375 @@
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/*******************************************************************************
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Intel(R) 82576 Virtual Function Linux driver
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Copyright(c) 1999 - 2008 Intel Corporation.
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This program is free software; you can redistribute it and/or modify it
7+
under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
11+
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12+
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13+
more details.
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You should have received a copy of the GNU General Public License along with
16+
this program; if not, write to the Free Software Foundation, Inc.,
17+
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18+
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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FILE_LICENCE ( GPL2_ONLY );
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/* Linux PRO/1000 Ethernet Driver main header file */
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#ifndef _IGBVF_H_
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#define _IGBVF_H_
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#include "igbvf_vf.h"
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/* Forward declarations */
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struct igbvf_info;
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struct igbvf_adapter;
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/* Interrupt defines */
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#define IGBVF_START_ITR 648 /* ~6000 ints/sec */
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/* Tx/Rx descriptor defines */
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#define IGBVF_DEFAULT_TXD 256
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#define IGBVF_MAX_TXD 4096
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#define IGBVF_MIN_TXD 80
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#define IGBVF_DEFAULT_RXD 256
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#define IGBVF_MAX_RXD 4096
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#define IGBVF_MIN_RXD 80
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#define IGBVF_MIN_ITR_USECS 10 /* 100000 irq/sec */
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#define IGBVF_MAX_ITR_USECS 10000 /* 100 irq/sec */
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/* RX descriptor control thresholds.
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* PTHRESH - MAC will consider prefetch if it has fewer than this number of
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* descriptors available in its onboard memory.
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* Setting this to 0 disables RX descriptor prefetch.
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* HTHRESH - MAC will only prefetch if there are at least this many descriptors
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* available in host memory.
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* If PTHRESH is 0, this should also be 0.
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* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
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* descriptors until either it has this many to write back, or the
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* ITR timer expires.
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*/
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#define IGBVF_RX_PTHRESH 16
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#define IGBVF_RX_HTHRESH 8
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#define IGBVF_RX_WTHRESH 1
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#define IGBVF_TX_PTHRESH 8
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#define IGBVF_TX_HTHRESH 1
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#define IGBVF_TX_WTHRESH 1
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/* this is the size past which hardware will drop packets when setting LPE=0 */
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#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
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#define IGBVF_FC_PAUSE_TIME 0x0680 /* 858 usec */
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/* How many Tx Descriptors do we need to call netif_wake_queue ? */
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#define IGBVF_TX_QUEUE_WAKE 32
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/* How many Rx Buffers do we bundle into one write to the hardware ? */
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#define IGBVF_RX_BUFFER_WRITE 16 /* Must be power of 2 */
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#define AUTO_ALL_MODES 0
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#define IGBVF_EEPROM_APME 0x0400
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#define IGBVF_MNG_VLAN_NONE (-1)
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enum igbvf_boards {
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board_vf,
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};
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struct igbvf_queue_stats {
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u64 packets;
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u64 bytes;
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};
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/*
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* wrappers around a pointer to a socket buffer,
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* so a DMA handle can be stored along with the buffer
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*/
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struct igbvf_buffer {
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dma_addr_t dma;
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dma_addr_t page_dma;
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struct sk_buff *skb;
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union {
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/* Tx */
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struct {
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unsigned long time_stamp;
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u16 length;
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u16 next_to_watch;
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};
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/* Rx */
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struct {
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struct page *page;
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unsigned int page_offset;
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};
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};
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struct page *page;
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};
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struct igbvf_ring {
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struct igbvf_adapter *adapter; /* backlink */
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void *desc; /* pointer to ring memory */
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dma_addr_t dma; /* phys address of ring */
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unsigned int size; /* length of ring in bytes */
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unsigned int count; /* number of desc. in ring */
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u16 next_to_use;
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u16 next_to_clean;
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u16 head;
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u16 tail;
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/* array of buffer information structs */
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struct igbvf_buffer *buffer_info;
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#if 0
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struct napi_struct napi;
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char name[IFNAMSIZ + 5];
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#endif
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u32 eims_value;
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u32 itr_val;
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u16 itr_register;
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int set_itr;
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struct sk_buff *rx_skb_top;
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struct igbvf_queue_stats stats;
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};
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/* board specific private data structure */
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struct igbvf_adapter {
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#if 0
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struct timer_list watchdog_timer;
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struct timer_list blink_timer;
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struct work_struct reset_task;
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struct work_struct watchdog_task;
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const struct igbvf_info *ei;
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struct vlan_group *vlgrp;
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u32 bd_number;
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u32 rx_buffer_len;
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u32 polling_interval;
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u16 mng_vlan_id;
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u16 link_speed;
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u16 link_duplex;
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spinlock_t tx_queue_lock; /* prevent concurrent tail updates */
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/* track device up/down/testing state */
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unsigned long state;
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/* Interrupt Throttle Rate */
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u32 itr;
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u32 itr_setting;
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u16 tx_itr;
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u16 rx_itr;
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/*
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* Tx
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*/
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struct igbvf_ring *tx_ring /* One per active queue */
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____cacheline_aligned_in_smp;
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unsigned long tx_queue_len;
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unsigned int restart_queue;
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u32 txd_cmd;
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bool detect_tx_hung;
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u8 tx_timeout_factor;
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unsigned int total_tx_bytes;
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unsigned int total_tx_packets;
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unsigned int total_rx_bytes;
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unsigned int total_rx_packets;
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/* Tx stats */
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u32 tx_timeout_count;
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u32 tx_fifo_head;
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u32 tx_head_addr;
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u32 tx_fifo_size;
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u32 tx_dma_failed;
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/*
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* Rx
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*/
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struct igbvf_ring *rx_ring;
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/* Rx stats */
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u64 hw_csum_err;
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u64 hw_csum_good;
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u64 rx_hdr_split;
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u32 alloc_rx_buff_failed;
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u32 rx_dma_failed;
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unsigned int rx_ps_hdr_size;
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u32 max_frame_size;
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u32 min_frame_size;
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/* OS defined structs */
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struct net_device *netdev;
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struct pci_dev *pdev;
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struct net_device_stats net_stats;
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spinlock_t stats_lock; /* prevent concurrent stats updates */
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/* structs defined in e1000_hw.h */
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struct e1000_hw hw;
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/* The VF counters don't clear on read so we have to get a base
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* count on driver start up and always subtract that base on
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* on the first update, thus the flag..
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*/
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struct e1000_vf_stats stats;
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u64 zero_base;
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struct igbvf_ring test_tx_ring;
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struct igbvf_ring test_rx_ring;
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u32 test_icr;
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u32 msg_enable;
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struct msix_entry *msix_entries;
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int int_mode;
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u32 eims_enable_mask;
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u32 eims_other;
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u32 int_counter0;
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u32 int_counter1;
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u32 eeprom_wol;
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u32 wol;
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u32 pba;
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bool fc_autoneg;
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unsigned long led_status;
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unsigned int flags;
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unsigned long last_reset;
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u32 *config_space;
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#endif
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/* OS defined structs */
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struct net_device *netdev;
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struct pci_device *pdev;
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struct net_device_stats net_stats;
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/* structs defined in e1000_hw.h */
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struct e1000_hw hw;
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u32 min_frame_size;
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u32 max_frame_size;
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u32 max_hw_frame_size;
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#define NUM_TX_DESC 8
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#define NUM_RX_DESC 8
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struct io_buffer *tx_iobuf[NUM_TX_DESC];
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struct io_buffer *rx_iobuf[NUM_RX_DESC];
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union e1000_adv_tx_desc *tx_base;
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union e1000_adv_rx_desc *rx_base;
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uint32_t tx_ring_size;
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uint32_t rx_ring_size;
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uint32_t tx_head;
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uint32_t tx_tail;
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uint32_t tx_fill_ctr;
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uint32_t rx_curr;
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uint32_t ioaddr;
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uint32_t irqno;
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uint32_t tx_int_delay;
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uint32_t tx_abs_int_delay;
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uint32_t txd_cmd;
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};
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struct igbvf_info {
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enum e1000_mac_type mac;
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unsigned int flags;
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u32 pba;
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void (*init_ops)(struct e1000_hw *);
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s32 (*get_variants)(struct igbvf_adapter *);
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};
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/* hardware capability, feature, and workaround flags */
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#define IGBVF_FLAG_RX_CSUM_DISABLED (1 << 0)
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#define IGBVF_DESC_UNUSED(R) \
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((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
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(R)->next_to_clean - (R)->next_to_use - 1)
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#define IGBVF_RX_DESC_ADV(R, i) \
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(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
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#define IGBVF_TX_DESC_ADV(R, i) \
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(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
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#define IGBVF_TX_CTXTDESC_ADV(R, i) \
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(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
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enum igbvf_state_t {
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__IGBVF_TESTING,
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__IGBVF_RESETTING,
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__IGBVF_DOWN
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};
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enum latency_range {
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lowest_latency = 0,
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low_latency = 1,
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bulk_latency = 2,
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latency_invalid = 255
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};
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extern char igbvf_driver_name[];
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extern const char igbvf_driver_version[];
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extern void igbvf_check_options(struct igbvf_adapter *adapter);
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extern void igbvf_set_ethtool_ops(struct net_device *netdev);
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#ifdef ETHTOOL_OPS_COMPAT
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extern int ethtool_ioctl(struct ifreq *ifr);
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#endif
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extern int igbvf_up(struct igbvf_adapter *adapter);
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extern void igbvf_down(struct igbvf_adapter *adapter);
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extern void igbvf_reinit_locked(struct igbvf_adapter *adapter);
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extern void igbvf_reset(struct igbvf_adapter *adapter);
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extern int igbvf_setup_rx_resources(struct igbvf_adapter *adapter);
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extern int igbvf_setup_tx_resources(struct igbvf_adapter *adapter);
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extern void igbvf_free_rx_resources(struct igbvf_adapter *adapter);
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extern void igbvf_free_tx_resources(struct igbvf_adapter *adapter);
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extern void igbvf_update_stats(struct igbvf_adapter *adapter);
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extern void igbvf_set_interrupt_capability(struct igbvf_adapter *adapter);
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extern void igbvf_reset_interrupt_capability(struct igbvf_adapter *adapter);
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extern unsigned int copybreak;
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static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
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{
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return readl(hw->hw_addr + reg);
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}
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static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
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{
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writel(val, hw->hw_addr + reg);
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}
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#define er32(reg) E1000_READ_REG(hw, E1000_##reg)
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#define ew32(reg,val) E1000_WRITE_REG(hw, E1000_##reg, (val))
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#define e1e_flush() er32(STATUS)
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#endif /* _IGBVF_H_ */

‎src/drivers/net/igbvf/igbvf_defines.h

+1,395
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‎src/drivers/net/igbvf/igbvf_main.c

+955
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‎src/drivers/net/igbvf/igbvf_mbx.c

+404
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‎src/drivers/net/igbvf/igbvf_mbx.h

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@@ -0,0 +1,87 @@
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/*******************************************************************************
2+
3+
Intel(R) 82576 Virtual Function Linux driver
4+
Copyright(c) 1999 - 2008 Intel Corporation.
5+
6+
This program is free software; you can redistribute it and/or modify it
7+
under the terms and conditions of the GNU General Public License,
8+
version 2, as published by the Free Software Foundation.
9+
10+
This program is distributed in the hope it will be useful, but WITHOUT
11+
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12+
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13+
more details.
14+
15+
You should have received a copy of the GNU General Public License along with
16+
this program; if not, write to the Free Software Foundation, Inc.,
17+
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18+
19+
The full GNU General Public License is included in this distribution in
20+
the file called "COPYING".
21+
22+
Contact Information:
23+
Linux NICS <linux.nics@intel.com>
24+
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25+
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26+
27+
*******************************************************************************/
28+
29+
FILE_LICENCE ( GPL2_ONLY );
30+
31+
#ifndef _IGBVF_MBX_H_
32+
#define _IGBVF_MBX_H_
33+
34+
#include "igbvf_vf.h"
35+
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/* Define mailbox specific registers */
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#define E1000_V2PMAILBOX(_n) (0x00C40 + (4 * (_n)))
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#define E1000_VMBMEM(_n) (0x00800 + (64 * (_n)))
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/* Define mailbox register bits */
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#define E1000_V2PMAILBOX_REQ 0x00000001 /* Request for PF Ready bit */
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#define E1000_V2PMAILBOX_ACK 0x00000002 /* Ack PF message received */
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#define E1000_V2PMAILBOX_VFU 0x00000004 /* VF owns the mailbox buffer */
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#define E1000_V2PMAILBOX_PFU 0x00000008 /* PF owns the mailbox buffer */
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#define E1000_V2PMAILBOX_PFSTS 0x00000010 /* PF wrote a message in the MB */
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#define E1000_V2PMAILBOX_PFACK 0x00000020 /* PF ack the previous VF msg */
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#define E1000_V2PMAILBOX_RSTI 0x00000040 /* PF has reset indication */
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#define E1000_V2PMAILBOX_RSTD 0x00000080 /* PF has indicated reset done */
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#define E1000_V2PMAILBOX_R2C_BITS 0x000000B0 /* All read to clear bits */
50+
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#define E1000_VFMAILBOX_SIZE 16 /* 16 32 bit words - 64 bytes */
52+
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/* If it's a E1000_VF_* msg then it originates in the VF and is sent to the
54+
* PF. The reverse is true if it is E1000_PF_*.
55+
* Message ACK's are the value or'd with 0xF0000000
56+
*/
57+
#define E1000_VT_MSGTYPE_ACK 0x80000000 /* Messages below or'd with
58+
* this are the ACK */
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#define E1000_VT_MSGTYPE_NACK 0x40000000 /* Messages below or'd with
60+
* this are the NACK */
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#define E1000_VT_MSGTYPE_CTS 0x20000000 /* Indicates that VF is still
62+
clear to send requests */
63+
#define E1000_VT_MSGINFO_SHIFT 16
64+
/* bits 23:16 are used for exra info for certain messages */
65+
#define E1000_VT_MSGINFO_MASK (0xFF << E1000_VT_MSGINFO_SHIFT)
66+
67+
#define E1000_VF_RESET 0x01 /* VF requests reset */
68+
#define E1000_VF_SET_MAC_ADDR 0x02 /* VF requests to set MAC addr */
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#define E1000_VF_SET_MULTICAST 0x03 /* VF requests to set MC addr */
70+
#define E1000_VF_SET_MULTICAST_COUNT_MASK (0x1F << E1000_VT_MSGINFO_SHIFT)
71+
#define E1000_VF_SET_MULTICAST_OVERFLOW (0x80 << E1000_VT_MSGINFO_SHIFT)
72+
#define E1000_VF_SET_VLAN 0x04 /* VF requests to set VLAN */
73+
#define E1000_VF_SET_VLAN_ADD (0x01 << E1000_VT_MSGINFO_SHIFT)
74+
#define E1000_VF_SET_LPE 0x05 /* VF requests to set VMOLR.LPE */
75+
#define E1000_VF_SET_PROMISC 0x06 /*VF requests to clear VMOLR.ROPE/MPME*/
76+
#define E1000_VF_SET_PROMISC_UNICAST (0x01 << E1000_VT_MSGINFO_SHIFT)
77+
#define E1000_VF_SET_PROMISC_MULTICAST (0x02 << E1000_VT_MSGINFO_SHIFT)
78+
79+
#define E1000_PF_CONTROL_MSG 0x0100 /* PF control message */
80+
81+
#define E1000_VF_MBX_INIT_TIMEOUT 2000 /* number of retries on mailbox */
82+
#define E1000_VF_MBX_INIT_DELAY 500 /* microseconds between retries */
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84+
void igbvf_init_mbx_ops_generic(struct e1000_hw *hw);
85+
s32 igbvf_init_mbx_params_vf(struct e1000_hw *);
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#endif /* _IGBVF_MBX_H_ */

‎src/drivers/net/igbvf/igbvf_osdep.h

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@@ -0,0 +1,121 @@
1+
/*******************************************************************************
2+
3+
Intel(R) 82576 Virtual Function Linux driver
4+
Copyright(c) 1999 - 2008 Intel Corporation.
5+
6+
This program is free software; you can redistribute it and/or modify it
7+
under the terms and conditions of the GNU General Public License,
8+
version 2, as published by the Free Software Foundation.
9+
10+
This program is distributed in the hope it will be useful, but WITHOUT
11+
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12+
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13+
more details.
14+
15+
You should have received a copy of the GNU General Public License along with
16+
this program; if not, write to the Free Software Foundation, Inc.,
17+
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18+
19+
The full GNU General Public License is included in this distribution in
20+
the file called "COPYING".
21+
22+
Contact Information:
23+
Linux NICS <linux.nics@intel.com>
24+
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25+
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26+
27+
*******************************************************************************/
28+
29+
FILE_LICENCE ( GPL2_ONLY );
30+
31+
/* glue for the OS-dependent part of igbvf
32+
* includes register access macros
33+
*/
34+
35+
#ifndef _IGBVF_OSDEP_H_
36+
#define _IGBVF_OSDEP_H_
37+
38+
#define u8 unsigned char
39+
#define bool boolean_t
40+
#define dma_addr_t unsigned long
41+
#define __le16 uint16_t
42+
#define __le32 uint32_t
43+
#define __le64 uint64_t
44+
45+
#define __iomem
46+
#define __devinit
47+
#define ____cacheline_aligned_in_smp
48+
49+
#define msleep(x) mdelay(x)
50+
51+
#define ETH_FCS_LEN 4
52+
53+
typedef int spinlock_t;
54+
typedef enum {
55+
false = 0,
56+
true = 1
57+
} boolean_t;
58+
59+
#define TRUE 1
60+
#define FALSE 0
61+
62+
#define usec_delay(x) udelay(x)
63+
#define msec_delay(x) mdelay(x)
64+
#define msec_delay_irq(x) mdelay(x)
65+
66+
#define PCI_COMMAND_REGISTER PCI_COMMAND
67+
#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
68+
#define ETH_ADDR_LEN ETH_ALEN
69+
70+
71+
#define DEBUGOUT(S) if (0) { printf(S); }
72+
#define DEBUGOUT1(S, A...) if (0) { printf(S, A); }
73+
74+
#define DEBUGFUNC(F) DEBUGOUT(F "\n")
75+
#define DEBUGOUT2 DEBUGOUT1
76+
#define DEBUGOUT3 DEBUGOUT2
77+
#define DEBUGOUT7 DEBUGOUT3
78+
79+
#define E1000_WRITE_REG(a, reg, value) do { \
80+
writel((value), ((a)->hw_addr + reg)); } while (0)
81+
82+
#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + reg))
83+
84+
#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) do { \
85+
writel((value), ((a)->hw_addr + reg + ((offset) << 2))); } while (0)
86+
87+
#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
88+
readl((a)->hw_addr + reg + ((offset) << 2)))
89+
90+
#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
91+
#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
92+
93+
#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
94+
writew((value), ((a)->hw_addr + reg + ((offset) << 1))))
95+
96+
#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
97+
readw((a)->hw_addr + reg + ((offset) << 1)))
98+
99+
#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
100+
writeb((value), ((a)->hw_addr + reg + (offset))))
101+
102+
#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
103+
readb((a)->hw_addr + reg + (offset)))
104+
105+
#define E1000_WRITE_REG_IO(a, reg, offset) do { \
106+
outl(reg, ((a)->io_base)); \
107+
outl(offset, ((a)->io_base + 4)); } while(0)
108+
109+
#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
110+
111+
#define E1000_WRITE_FLASH_REG(a, reg, value) ( \
112+
writel((value), ((a)->flash_address + reg)))
113+
114+
#define E1000_WRITE_FLASH_REG16(a, reg, value) ( \
115+
writew((value), ((a)->flash_address + reg)))
116+
117+
#define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg))
118+
119+
#define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg))
120+
121+
#endif /* _IGBVF_OSDEP_H_ */

‎src/drivers/net/igbvf/igbvf_regs.h

+338
Large diffs are not rendered by default.

‎src/drivers/net/igbvf/igbvf_vf.c

+455
Large diffs are not rendered by default.

‎src/drivers/net/igbvf/igbvf_vf.h

+345
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,345 @@
1+
/*******************************************************************************
2+
3+
Intel(R) 82576 Virtual Function Linux driver
4+
Copyright(c) 1999 - 2008 Intel Corporation.
5+
6+
This program is free software; you can redistribute it and/or modify it
7+
under the terms and conditions of the GNU General Public License,
8+
version 2, as published by the Free Software Foundation.
9+
10+
This program is distributed in the hope it will be useful, but WITHOUT
11+
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12+
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13+
more details.
14+
15+
You should have received a copy of the GNU General Public License along with
16+
this program; if not, write to the Free Software Foundation, Inc.,
17+
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18+
19+
The full GNU General Public License is included in this distribution in
20+
the file called "COPYING".
21+
22+
Contact Information:
23+
Linux NICS <linux.nics@intel.com>
24+
e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25+
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26+
27+
*******************************************************************************/
28+
29+
FILE_LICENCE ( GPL2_ONLY );
30+
31+
#ifndef _IGBVF_VF_H_
32+
#define _IGBVF_VF_H_
33+
34+
#include <stddef.h>
35+
#include <stdint.h>
36+
#include <stdlib.h>
37+
#include <stdio.h>
38+
#include <string.h>
39+
#include <unistd.h>
40+
#include <byteswap.h>
41+
#include <errno.h>
42+
#include <ipxe/pci.h>
43+
#include <ipxe/malloc.h>
44+
#include <ipxe/if_ether.h>
45+
#include <ipxe/io.h>
46+
#include <ipxe/ethernet.h>
47+
#include <ipxe/iobuf.h>
48+
#include <ipxe/netdevice.h>
49+
50+
#include "igbvf_osdep.h"
51+
#include "igbvf_regs.h"
52+
#include "igbvf_defines.h"
53+
54+
struct e1000_hw;
55+
56+
#define E1000_DEV_ID_82576_VF 0x10CA
57+
58+
#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
59+
60+
/* Additional Descriptor Control definitions */
61+
#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
62+
#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
63+
64+
/* SRRCTL bit definitions */
65+
#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
66+
#define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00
67+
#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
68+
#define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000
69+
#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
70+
#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
71+
#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
72+
#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000
73+
#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
74+
#define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000
75+
#define E1000_SRRCTL_DROP_EN 0x80000000
76+
77+
#define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F
78+
#define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00
79+
80+
/* Interrupt Defines */
81+
#define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
82+
#define E1000_EITR(_n) (0x01680 + ((_n) << 2))
83+
#define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
84+
#define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
85+
#define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
86+
#define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
87+
#define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
88+
#define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
89+
#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
90+
#define E1000_IVAR_VALID 0x80
91+
92+
/* Receive Descriptor - Advanced */
93+
union e1000_adv_rx_desc {
94+
struct {
95+
u64 pkt_addr; /* Packet buffer address */
96+
u64 hdr_addr; /* Header buffer address */
97+
} read;
98+
struct {
99+
struct {
100+
union {
101+
u32 data;
102+
struct {
103+
u16 pkt_info; /* RSS type, Packet type */
104+
u16 hdr_info; /* Split Header,
105+
* header buffer length */
106+
} hs_rss;
107+
} lo_dword;
108+
union {
109+
u32 rss; /* RSS Hash */
110+
struct {
111+
u16 ip_id; /* IP id */
112+
u16 csum; /* Packet Checksum */
113+
} csum_ip;
114+
} hi_dword;
115+
} lower;
116+
struct {
117+
u32 status_error; /* ext status/error */
118+
u16 length; /* Packet length */
119+
u16 vlan; /* VLAN tag */
120+
} upper;
121+
} wb; /* writeback */
122+
};
123+
124+
#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
125+
#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
126+
127+
/* Transmit Descriptor - Advanced */
128+
union e1000_adv_tx_desc {
129+
struct {
130+
u64 buffer_addr; /* Address of descriptor's data buf */
131+
u32 cmd_type_len;
132+
u32 olinfo_status;
133+
} read;
134+
struct {
135+
u64 rsvd; /* Reserved */
136+
u32 nxtseq_seed;
137+
u32 status;
138+
} wb;
139+
};
140+
141+
/* Adv Transmit Descriptor Config Masks */
142+
#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
143+
#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
144+
#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
145+
#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
146+
#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
147+
#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
148+
#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
149+
#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
150+
#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
151+
152+
/* Context descriptors */
153+
struct e1000_adv_tx_context_desc {
154+
u32 vlan_macip_lens;
155+
u32 seqnum_seed;
156+
u32 type_tucmd_mlhl;
157+
u32 mss_l4len_idx;
158+
};
159+
160+
#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
161+
#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
162+
#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
163+
#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
164+
#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
165+
166+
enum e1000_mac_type {
167+
e1000_undefined = 0,
168+
e1000_vfadapt,
169+
e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
170+
};
171+
172+
struct e1000_vf_stats {
173+
u64 base_gprc;
174+
u64 base_gptc;
175+
u64 base_gorc;
176+
u64 base_gotc;
177+
u64 base_mprc;
178+
u64 base_gotlbc;
179+
u64 base_gptlbc;
180+
u64 base_gorlbc;
181+
u64 base_gprlbc;
182+
183+
u32 last_gprc;
184+
u32 last_gptc;
185+
u32 last_gorc;
186+
u32 last_gotc;
187+
u32 last_mprc;
188+
u32 last_gotlbc;
189+
u32 last_gptlbc;
190+
u32 last_gorlbc;
191+
u32 last_gprlbc;
192+
193+
u64 gprc;
194+
u64 gptc;
195+
u64 gorc;
196+
u64 gotc;
197+
u64 mprc;
198+
u64 gotlbc;
199+
u64 gptlbc;
200+
u64 gorlbc;
201+
u64 gprlbc;
202+
};
203+
204+
#include "igbvf_mbx.h"
205+
206+
struct e1000_mac_operations {
207+
/* Function pointers for the MAC. */
208+
s32 (*init_params)(struct e1000_hw *);
209+
s32 (*check_for_link)(struct e1000_hw *);
210+
void (*clear_vfta)(struct e1000_hw *);
211+
s32 (*get_bus_info)(struct e1000_hw *);
212+
s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
213+
void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
214+
s32 (*reset_hw)(struct e1000_hw *);
215+
s32 (*init_hw)(struct e1000_hw *);
216+
s32 (*setup_link)(struct e1000_hw *);
217+
void (*write_vfta)(struct e1000_hw *, u32, u32);
218+
void (*mta_set)(struct e1000_hw *, u32);
219+
void (*rar_set)(struct e1000_hw *, u8*, u32);
220+
s32 (*read_mac_addr)(struct e1000_hw *);
221+
};
222+
223+
struct e1000_mac_info {
224+
struct e1000_mac_operations ops;
225+
u8 addr[6];
226+
u8 perm_addr[6];
227+
228+
enum e1000_mac_type type;
229+
230+
u16 mta_reg_count;
231+
u16 rar_entry_count;
232+
233+
bool get_link_status;
234+
};
235+
236+
enum e1000_bus_type {
237+
e1000_bus_type_unknown = 0,
238+
e1000_bus_type_pci,
239+
e1000_bus_type_pcix,
240+
e1000_bus_type_pci_express,
241+
e1000_bus_type_reserved
242+
};
243+
244+
enum e1000_bus_speed {
245+
e1000_bus_speed_unknown = 0,
246+
e1000_bus_speed_33,
247+
e1000_bus_speed_66,
248+
e1000_bus_speed_100,
249+
e1000_bus_speed_120,
250+
e1000_bus_speed_133,
251+
e1000_bus_speed_2500,
252+
e1000_bus_speed_5000,
253+
e1000_bus_speed_reserved
254+
};
255+
256+
enum e1000_bus_width {
257+
e1000_bus_width_unknown = 0,
258+
e1000_bus_width_pcie_x1,
259+
e1000_bus_width_pcie_x2,
260+
e1000_bus_width_pcie_x4 = 4,
261+
e1000_bus_width_pcie_x8 = 8,
262+
e1000_bus_width_32,
263+
e1000_bus_width_64,
264+
e1000_bus_width_reserved
265+
};
266+
267+
struct e1000_bus_info {
268+
enum e1000_bus_type type;
269+
enum e1000_bus_speed speed;
270+
enum e1000_bus_width width;
271+
272+
u16 func;
273+
u16 pci_cmd_word;
274+
};
275+
276+
struct e1000_mbx_operations {
277+
s32 (*init_params)(struct e1000_hw *hw);
278+
s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
279+
s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
280+
s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
281+
s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
282+
s32 (*check_for_msg)(struct e1000_hw *, u16);
283+
s32 (*check_for_ack)(struct e1000_hw *, u16);
284+
s32 (*check_for_rst)(struct e1000_hw *, u16);
285+
};
286+
287+
struct e1000_mbx_stats {
288+
u32 msgs_tx;
289+
u32 msgs_rx;
290+
291+
u32 acks;
292+
u32 reqs;
293+
u32 rsts;
294+
};
295+
296+
struct e1000_mbx_info {
297+
struct e1000_mbx_operations ops;
298+
struct e1000_mbx_stats stats;
299+
u32 timeout;
300+
u32 usec_delay;
301+
u16 size;
302+
};
303+
304+
struct e1000_dev_spec_vf {
305+
u32 vf_number;
306+
u32 v2p_mailbox;
307+
};
308+
309+
struct e1000_hw {
310+
void *back;
311+
312+
u8 __iomem *hw_addr;
313+
u8 __iomem *flash_address;
314+
unsigned long io_base;
315+
316+
struct e1000_mac_info mac;
317+
struct e1000_bus_info bus;
318+
struct e1000_mbx_info mbx;
319+
320+
union {
321+
struct e1000_dev_spec_vf vf;
322+
} dev_spec;
323+
324+
u16 device_id;
325+
u16 subsystem_vendor_id;
326+
u16 subsystem_device_id;
327+
u16 vendor_id;
328+
329+
u8 revision_id;
330+
};
331+
332+
enum e1000_promisc_type {
333+
e1000_promisc_disabled = 0, /* all promisc modes disabled */
334+
e1000_promisc_unicast = 1, /* unicast promiscuous enabled */
335+
e1000_promisc_multicast = 2, /* multicast promiscuous enabled */
336+
e1000_promisc_enabled = 3, /* both uni and multicast promisc */
337+
e1000_num_promisc_types
338+
};
339+
340+
/* These functions must be implemented by drivers */
341+
s32 igbvf_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
342+
void igbvf_vfta_set_vf(struct e1000_hw *, u16, bool);
343+
void igbvf_rlpml_set_vf(struct e1000_hw *, u16);
344+
s32 igbvf_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type);
345+
#endif /* _IGBVF_VF_H_ */

‎src/include/ipxe/errfile.h

+1
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,7 @@ FILE_LICENCE ( GPL2_OR_LATER );
135135
#define ERRFILE_jme ( ERRFILE_DRIVER | 0x005b0000 )
136136
#define ERRFILE_virtio_net ( ERRFILE_DRIVER | 0x005c0000 )
137137
#define ERRFILE_tap ( ERRFILE_DRIVER | 0x005d0000 )
138+
#define ERRFILE_igbvf_main ( ERRFILE_DRIVER | 0x005e0000 )
138139

139140
#define ERRFILE_scsi ( ERRFILE_DRIVER | 0x00700000 )
140141
#define ERRFILE_arbel ( ERRFILE_DRIVER | 0x00710000 )

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