[realtek] Ensure EEPROM writes reach chip before starting udelay()

On some systems, it appears to be possible for writes to the EEPROM registers to be delayed for long enough that the EEPROM's setup and hold times are violated, resulting in invalid data being read from the EEPROM. Fix by inserting a PCI read cycle immediately after writes to RTL_9346CR, to ensure that the write has completed before starting the udelay() used to time the SPI bus transitions. Reported-by: Gelip <mrgelip@gmail.com> Tested-by: Gelip <mrgelip@gmail.com> Signed-off-by: Michael Brown <mcb30@ipxe.org>
ipxe · May 1, 2013 · 9b1ec31 · 9b1ec31
1 parent c6375a8
commit 9b1ec31
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/src/drivers/net/realtek.c b/src/drivers/net/realtek.c
@@ -74,6 +74,7 @@ static void realtek_spi_open_bit ( struct bit_basher *basher ) {
 
 	/* Enable EEPROM access */
 	writeb ( RTL_9346CR_EEM_EEPROM, rtl->regs + RTL_9346CR );
+	readb ( rtl->regs + RTL_9346CR ); /* Ensure write reaches chip */
 }
 
 /**
@@ -87,6 +88,7 @@ static void realtek_spi_close_bit ( struct bit_basher *basher ) {
 
 	/* Disable EEPROM access */
 	writeb ( RTL_9346CR_EEM_NORMAL, rtl->regs + RTL_9346CR );
+	readb ( rtl->regs + RTL_9346CR ); /* Ensure write reaches chip */
 }
 
 /**
@@ -129,6 +131,7 @@ static void realtek_spi_write_bit ( struct bit_basher *basher,
 	reg &= ~mask;
 	reg |= ( data & mask );
 	writeb ( reg, rtl->regs + RTL_9346CR );
+	readb ( rtl->regs + RTL_9346CR ); /* Ensure write reaches chip */
 	DBG_ENABLE ( DBGLVL_IO );
 }