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phantom.c
2405 lines (2115 loc) · 68.2 KB
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phantom.c
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/*
* Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
* Copyright (C) 2008 NetXen, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <errno.h>
#include <assert.h>
#include <byteswap.h>
#include <gpxe/pci.h>
#include <gpxe/io.h>
#include <gpxe/malloc.h>
#include <gpxe/iobuf.h>
#include <gpxe/netdevice.h>
#include <gpxe/if_ether.h>
#include <gpxe/ethernet.h>
#include <gpxe/spi.h>
#include <gpxe/settings.h>
#include "phantom.h"
/**
* @file
*
* NetXen Phantom NICs
*
*/
/** Maximum time to wait for SPI lock */
#define PHN_SPI_LOCK_TIMEOUT_MS 100
/** Maximum time to wait for SPI command to be issued */
#define PHN_SPI_CMD_TIMEOUT_MS 100
/** Maximum time to wait for command PEG to initialise
*
* BUGxxxx
*
* The command PEG will currently report initialisation complete only
* when at least one PHY has detected a link (so that the global PHY
* clock can be set to 10G/1G as appropriate). This can take a very,
* very long time.
*
* A future firmware revision should decouple PHY initialisation from
* firmware initialisation, at which point the command PEG will report
* initialisation complete much earlier, and this timeout can be
* reduced.
*/
#define PHN_CMDPEG_INIT_TIMEOUT_SEC 50
/** Maximum time to wait for receive PEG to initialise */
#define PHN_RCVPEG_INIT_TIMEOUT_SEC 2
/** Maximum time to wait for firmware to accept a command */
#define PHN_ISSUE_CMD_TIMEOUT_MS 2000
/** Maximum time to wait for test memory */
#define PHN_TEST_MEM_TIMEOUT_MS 100
/** Maximum time to wait for CLP command to be issued */
#define PHN_CLP_CMD_TIMEOUT_MS 500
/** Link state poll frequency
*
* The link state will be checked once in every N calls to poll().
*/
#define PHN_LINK_POLL_FREQUENCY 4096
/** Number of RX descriptors */
#define PHN_NUM_RDS 32
/** RX maximum fill level. Must be strictly less than PHN_NUM_RDS. */
#define PHN_RDS_MAX_FILL 16
/** RX buffer size */
#define PHN_RX_BUFSIZE ( 32 /* max LL padding added by card */ + \
ETH_FRAME_LEN )
/** Number of RX status descriptors */
#define PHN_NUM_SDS 32
/** Number of TX descriptors */
#define PHN_NUM_CDS 8
/** A Phantom descriptor ring set */
struct phantom_descriptor_rings {
/** RX descriptors */
struct phantom_rds rds[PHN_NUM_RDS];
/** RX status descriptors */
struct phantom_sds sds[PHN_NUM_SDS];
/** TX descriptors */
union phantom_cds cds[PHN_NUM_CDS];
/** TX consumer index */
volatile uint32_t cmd_cons;
};
/** A Phantom NIC port */
struct phantom_nic_port {
/** Phantom NIC containing this port */
struct phantom_nic *phantom;
/** Port number */
unsigned int port;
/** RX context ID */
uint16_t rx_context_id;
/** RX descriptor producer CRB offset */
unsigned long rds_producer_crb;
/** RX status descriptor consumer CRB offset */
unsigned long sds_consumer_crb;
/** RX producer index */
unsigned int rds_producer_idx;
/** RX consumer index */
unsigned int rds_consumer_idx;
/** RX status consumer index */
unsigned int sds_consumer_idx;
/** RX I/O buffers */
struct io_buffer *rds_iobuf[PHN_RDS_MAX_FILL];
/** TX context ID */
uint16_t tx_context_id;
/** TX descriptor producer CRB offset */
unsigned long cds_producer_crb;
/** TX producer index */
unsigned int cds_producer_idx;
/** TX consumer index */
unsigned int cds_consumer_idx;
/** TX I/O buffers */
struct io_buffer *cds_iobuf[PHN_NUM_CDS];
/** Link state poll timer */
unsigned long link_poll_timer;
/** Descriptor rings */
struct phantom_descriptor_rings *desc;
/** Non-volatile settings */
struct settings settings;
};
/** RX context creation request and response buffers */
struct phantom_create_rx_ctx_rqrsp {
struct {
struct nx_hostrq_rx_ctx_s rx_ctx;
struct nx_hostrq_rds_ring_s rds;
struct nx_hostrq_sds_ring_s sds;
} __unm_dma_aligned hostrq;
struct {
struct nx_cardrsp_rx_ctx_s rx_ctx;
struct nx_cardrsp_rds_ring_s rds;
struct nx_cardrsp_sds_ring_s sds;
} __unm_dma_aligned cardrsp;
};
/** TX context creation request and response buffers */
struct phantom_create_tx_ctx_rqrsp {
struct {
struct nx_hostrq_tx_ctx_s tx_ctx;
} __unm_dma_aligned hostrq;
struct {
struct nx_cardrsp_tx_ctx_s tx_ctx;
} __unm_dma_aligned cardrsp;
};
/** A Phantom DMA buffer area */
union phantom_dma_buffer {
/** Dummy area required for (read-only) self-tests */
uint8_t dummy_dma[UNM_DUMMY_DMA_SIZE];
/** RX context creation request and response buffers */
struct phantom_create_rx_ctx_rqrsp create_rx_ctx;
/** TX context creation request and response buffers */
struct phantom_create_tx_ctx_rqrsp create_tx_ctx;
};
/** A Phantom NIC */
struct phantom_nic {
/** BAR 0 */
void *bar0;
/** Current CRB window */
unsigned long crb_window;
/** CRB window access method */
unsigned long ( *crb_access ) ( struct phantom_nic *phantom,
unsigned long reg );
/** Number of ports */
int num_ports;
/** Per-port network devices */
struct net_device *netdev[UNM_FLASH_NUM_PORTS];
/** DMA buffers */
union phantom_dma_buffer *dma_buf;
/** Flash memory SPI bus */
struct spi_bus spi_bus;
/** Flash memory SPI device */
struct spi_device flash;
/** Last known link state */
uint32_t link_state;
};
/***************************************************************************
*
* CRB register access
*
*/
/**
* Prepare for access to CRB register via 128MB BAR
*
* @v phantom Phantom NIC
* @v reg Register offset within abstract address space
* @ret offset Register offset within PCI BAR0
*/
static unsigned long phantom_crb_access_128m ( struct phantom_nic *phantom,
unsigned long reg ) {
unsigned long offset = ( 0x6000000 + ( reg & 0x1ffffff ) );
uint32_t window = ( reg & 0x2000000 );
uint32_t verify_window;
if ( phantom->crb_window != window ) {
/* Write to the CRB window register */
writel ( window, phantom->bar0 + UNM_128M_CRB_WINDOW );
/* Ensure that the write has reached the card */
verify_window = readl ( phantom->bar0 + UNM_128M_CRB_WINDOW );
assert ( verify_window == window );
/* Record new window */
phantom->crb_window = window;
}
return offset;
}
/**
* Prepare for access to CRB register via 32MB BAR
*
* @v phantom Phantom NIC
* @v reg Register offset within abstract address space
* @ret offset Register offset within PCI BAR0
*/
static unsigned long phantom_crb_access_32m ( struct phantom_nic *phantom,
unsigned long reg ) {
unsigned long offset = ( reg & 0x1ffffff );
uint32_t window = ( reg & 0x2000000 );
uint32_t verify_window;
if ( phantom->crb_window != window ) {
/* Write to the CRB window register */
writel ( window, phantom->bar0 + UNM_32M_CRB_WINDOW );
/* Ensure that the write has reached the card */
verify_window = readl ( phantom->bar0 + UNM_32M_CRB_WINDOW );
assert ( verify_window == window );
/* Record new window */
phantom->crb_window = window;
}
return offset;
}
/**
* Prepare for access to CRB register via 2MB BAR
*
* @v phantom Phantom NIC
* @v reg Register offset within abstract address space
* @ret offset Register offset within PCI BAR0
*/
static unsigned long phantom_crb_access_2m ( struct phantom_nic *phantom,
unsigned long reg ) {
static const struct {
uint8_t block;
uint16_t window_hi;
} reg_window_hi[] = {
{ UNM_CRB_BLK_PCIE, 0x773 },
{ UNM_CRB_BLK_CAM, 0x416 },
{ UNM_CRB_BLK_ROMUSB, 0x421 },
{ UNM_CRB_BLK_TEST, 0x295 },
{ UNM_CRB_BLK_PEG_0, 0x340 },
{ UNM_CRB_BLK_PEG_1, 0x341 },
{ UNM_CRB_BLK_PEG_2, 0x342 },
{ UNM_CRB_BLK_PEG_3, 0x343 },
{ UNM_CRB_BLK_PEG_4, 0x34b },
};
unsigned int block = UNM_CRB_BLK ( reg );
unsigned long offset = UNM_CRB_OFFSET ( reg );
uint32_t window;
uint32_t verify_window;
unsigned int i;
for ( i = 0 ; i < ( sizeof ( reg_window_hi ) /
sizeof ( reg_window_hi[0] ) ) ; i++ ) {
if ( reg_window_hi[i].block != block )
continue;
window = ( ( reg_window_hi[i].window_hi << 20 ) |
( offset & 0x000f0000 ) );
if ( phantom->crb_window != window ) {
/* Write to the CRB window register */
writel ( window, phantom->bar0 + UNM_2M_CRB_WINDOW );
/* Ensure that the write has reached the card */
verify_window = readl ( phantom->bar0 +
UNM_2M_CRB_WINDOW );
assert ( verify_window == window );
/* Record new window */
phantom->crb_window = window;
}
return ( 0x1e0000 + ( offset & 0xffff ) );
}
assert ( 0 );
return 0;
}
/**
* Read from Phantom CRB register
*
* @v phantom Phantom NIC
* @v reg Register offset within abstract address space
* @ret value Register value
*/
static uint32_t phantom_readl ( struct phantom_nic *phantom,
unsigned long reg ) {
unsigned long offset;
offset = phantom->crb_access ( phantom, reg );
return readl ( phantom->bar0 + offset );
}
/**
* Write to Phantom CRB register
*
* @v phantom Phantom NIC
* @v value Register value
* @v reg Register offset within abstract address space
*/
static void phantom_writel ( struct phantom_nic *phantom, uint32_t value,
unsigned long reg ) {
unsigned long offset;
offset = phantom->crb_access ( phantom, reg );
writel ( value, phantom->bar0 + offset );
}
/**
* Write to Phantom CRB HI/LO register pair
*
* @v phantom Phantom NIC
* @v value Register value
* @v lo_offset LO register offset within CRB
* @v hi_offset HI register offset within CRB
*/
static inline void phantom_write_hilo ( struct phantom_nic *phantom,
uint64_t value,
unsigned long lo_offset,
unsigned long hi_offset ) {
uint32_t lo = ( value & 0xffffffffUL );
uint32_t hi = ( value >> 32 );
phantom_writel ( phantom, lo, lo_offset );
phantom_writel ( phantom, hi, hi_offset );
}
/***************************************************************************
*
* Firmware message buffer access (for debug)
*
*/
/**
* Read from Phantom test memory
*
* @v phantom Phantom NIC
* @v offset Offset within test memory
* @v buf 8-byte buffer to fill
* @ret rc Return status code
*/
static int phantom_read_test_mem_block ( struct phantom_nic *phantom,
unsigned long offset,
uint32_t buf[2] ) {
unsigned int retries;
uint32_t test_control;
phantom_write_hilo ( phantom, offset, UNM_TEST_ADDR_LO,
UNM_TEST_ADDR_HI );
phantom_writel ( phantom, UNM_TEST_CONTROL_ENABLE, UNM_TEST_CONTROL );
phantom_writel ( phantom,
( UNM_TEST_CONTROL_ENABLE | UNM_TEST_CONTROL_START ),
UNM_TEST_CONTROL );
for ( retries = 0 ; retries < PHN_TEST_MEM_TIMEOUT_MS ; retries++ ) {
test_control = phantom_readl ( phantom, UNM_TEST_CONTROL );
if ( ( test_control & UNM_TEST_CONTROL_BUSY ) == 0 ) {
buf[0] = phantom_readl ( phantom, UNM_TEST_RDDATA_LO );
buf[1] = phantom_readl ( phantom, UNM_TEST_RDDATA_HI );
return 0;
}
mdelay ( 1 );
}
DBGC ( phantom, "Phantom %p timed out waiting for test memory\n",
phantom );
return -ETIMEDOUT;
}
/**
* Read single byte from Phantom test memory
*
* @v phantom Phantom NIC
* @v offset Offset within test memory
* @ret byte Byte read, or negative error
*/
static int phantom_read_test_mem ( struct phantom_nic *phantom,
unsigned long offset ) {
static union {
uint8_t bytes[8];
uint32_t dwords[2];
} cache;
static unsigned long cache_offset = -1UL;
unsigned long sub_offset;
int rc;
sub_offset = ( offset & ( sizeof ( cache ) - 1 ) );
offset = ( offset & ~( sizeof ( cache ) - 1 ) );
if ( cache_offset != offset ) {
if ( ( rc = phantom_read_test_mem_block ( phantom, offset,
cache.dwords )) !=0 )
return rc;
cache_offset = offset;
}
return cache.bytes[sub_offset];
}
/**
* Dump Phantom firmware dmesg log
*
* @v phantom Phantom NIC
* @v log Log number
* @v max_lines Maximum number of lines to show, or -1 to show all
* @ret rc Return status code
*/
static int phantom_dmesg ( struct phantom_nic *phantom, unsigned int log,
unsigned int max_lines ) {
uint32_t head;
uint32_t tail;
uint32_t len;
uint32_t sig;
uint32_t offset;
int byte;
/* Optimise out for non-debug builds */
if ( ! DBG_LOG )
return 0;
/* Locate log */
head = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_HEAD ( log ) );
len = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_LEN ( log ) );
tail = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_TAIL ( log ) );
sig = phantom_readl ( phantom, UNM_CAM_RAM_DMESG_SIG ( log ) );
DBGC ( phantom, "Phantom %p firmware dmesg buffer %d (%08lx-%08lx)\n",
phantom, log, head, tail );
assert ( ( head & 0x07 ) == 0 );
if ( sig != UNM_CAM_RAM_DMESG_SIG_MAGIC ) {
DBGC ( phantom, "Warning: bad signature %08lx (want %08lx)\n",
sig, UNM_CAM_RAM_DMESG_SIG_MAGIC );
}
/* Locate start of last (max_lines) lines */
for ( offset = tail ; offset > head ; offset-- ) {
if ( ( byte = phantom_read_test_mem ( phantom,
( offset - 1 ) ) ) < 0 )
return byte;
if ( ( byte == '\n' ) && ( max_lines-- == 0 ) )
break;
}
/* Print lines */
for ( ; offset < tail ; offset++ ) {
if ( ( byte = phantom_read_test_mem ( phantom, offset ) ) < 0 )
return byte;
DBG ( "%c", byte );
}
DBG ( "\n" );
return 0;
}
/**
* Dump Phantom firmware dmesg logs
*
* @v phantom Phantom NIC
* @v max_lines Maximum number of lines to show, or -1 to show all
*/
static void __attribute__ (( unused ))
phantom_dmesg_all ( struct phantom_nic *phantom, unsigned int max_lines ) {
unsigned int i;
for ( i = 0 ; i < UNM_CAM_RAM_NUM_DMESG_BUFFERS ; i++ )
phantom_dmesg ( phantom, i, max_lines );
}
/***************************************************************************
*
* SPI bus access (for flash memory)
*
*/
/**
* Acquire Phantom SPI lock
*
* @v phantom Phantom NIC
* @ret rc Return status code
*/
static int phantom_spi_lock ( struct phantom_nic *phantom ) {
unsigned int retries;
uint32_t pcie_sem2_lock;
for ( retries = 0 ; retries < PHN_SPI_LOCK_TIMEOUT_MS ; retries++ ) {
pcie_sem2_lock = phantom_readl ( phantom, UNM_PCIE_SEM2_LOCK );
if ( pcie_sem2_lock != 0 )
return 0;
mdelay ( 1 );
}
DBGC ( phantom, "Phantom %p timed out waiting for SPI lock\n",
phantom );
return -ETIMEDOUT;
}
/**
* Wait for Phantom SPI command to complete
*
* @v phantom Phantom NIC
* @ret rc Return status code
*/
static int phantom_spi_wait ( struct phantom_nic *phantom ) {
unsigned int retries;
uint32_t glb_status;
for ( retries = 0 ; retries < PHN_SPI_CMD_TIMEOUT_MS ; retries++ ) {
glb_status = phantom_readl ( phantom, UNM_ROMUSB_GLB_STATUS );
if ( glb_status & UNM_ROMUSB_GLB_STATUS_ROM_DONE )
return 0;
mdelay ( 1 );
}
DBGC ( phantom, "Phantom %p timed out waiting for SPI command\n",
phantom );
return -ETIMEDOUT;
}
/**
* Release Phantom SPI lock
*
* @v phantom Phantom NIC
*/
static void phantom_spi_unlock ( struct phantom_nic *phantom ) {
phantom_readl ( phantom, UNM_PCIE_SEM2_UNLOCK );
}
/**
* Read/write data via Phantom SPI bus
*
* @v bus SPI bus
* @v device SPI device
* @v command Command
* @v address Address to read/write (<0 for no address)
* @v data_out TX data buffer (or NULL)
* @v data_in RX data buffer (or NULL)
* @v len Length of data buffer(s)
* @ret rc Return status code
*/
static int phantom_spi_rw ( struct spi_bus *bus,
struct spi_device *device,
unsigned int command, int address,
const void *data_out, void *data_in,
size_t len ) {
struct phantom_nic *phantom =
container_of ( bus, struct phantom_nic, spi_bus );
uint32_t data;
int rc;
DBGCP ( phantom, "Phantom %p SPI command %x at %x+%zx\n",
phantom, command, address, len );
if ( data_out )
DBGCP_HDA ( phantom, address, data_out, len );
/* We support only exactly 4-byte reads */
if ( len != UNM_SPI_BLKSIZE ) {
DBGC ( phantom, "Phantom %p invalid SPI length %zx\n",
phantom, len );
return -EINVAL;
}
/* Acquire SPI lock */
if ( ( rc = phantom_spi_lock ( phantom ) ) != 0 )
goto err_lock;
/* Issue SPI command as per the PRM */
if ( data_out ) {
memcpy ( &data, data_out, sizeof ( data ) );
phantom_writel ( phantom, data, UNM_ROMUSB_ROM_WDATA );
}
phantom_writel ( phantom, address, UNM_ROMUSB_ROM_ADDRESS );
phantom_writel ( phantom, ( device->address_len / 8 ),
UNM_ROMUSB_ROM_ABYTE_CNT );
udelay ( 100 ); /* according to PRM */
phantom_writel ( phantom, 0, UNM_ROMUSB_ROM_DUMMY_BYTE_CNT );
phantom_writel ( phantom, command, UNM_ROMUSB_ROM_INSTR_OPCODE );
/* Wait for SPI command to complete */
if ( ( rc = phantom_spi_wait ( phantom ) ) != 0 )
goto err_wait;
/* Reset address byte count and dummy byte count, because the
* PRM asks us to.
*/
phantom_writel ( phantom, 0, UNM_ROMUSB_ROM_ABYTE_CNT );
udelay ( 100 ); /* according to PRM */
phantom_writel ( phantom, 0, UNM_ROMUSB_ROM_DUMMY_BYTE_CNT );
/* Read data, if applicable */
if ( data_in ) {
data = phantom_readl ( phantom, UNM_ROMUSB_ROM_RDATA );
memcpy ( data_in, &data, sizeof ( data ) );
DBGCP_HDA ( phantom, address, data_in, len );
}
err_wait:
phantom_spi_unlock ( phantom );
err_lock:
return rc;
}
/***************************************************************************
*
* Firmware interface
*
*/
/**
* Wait for firmware to accept command
*
* @v phantom Phantom NIC
* @ret rc Return status code
*/
static int phantom_wait_for_cmd ( struct phantom_nic *phantom ) {
unsigned int retries;
uint32_t cdrp;
for ( retries = 0 ; retries < PHN_ISSUE_CMD_TIMEOUT_MS ; retries++ ) {
mdelay ( 1 );
cdrp = phantom_readl ( phantom, UNM_NIC_REG_NX_CDRP );
if ( NX_CDRP_IS_RSP ( cdrp ) ) {
switch ( NX_CDRP_FORM_RSP ( cdrp ) ) {
case NX_CDRP_RSP_OK:
return 0;
case NX_CDRP_RSP_FAIL:
return -EIO;
case NX_CDRP_RSP_TIMEOUT:
return -ETIMEDOUT;
default:
return -EPROTO;
}
}
}
DBGC ( phantom, "Phantom %p timed out waiting for firmware to accept "
"command\n", phantom );
return -ETIMEDOUT;
}
/**
* Issue command to firmware
*
* @v phantom_port Phantom NIC port
* @v command Firmware command
* @v arg1 Argument 1
* @v arg2 Argument 2
* @v arg3 Argument 3
* @ret rc Return status code
*/
static int phantom_issue_cmd ( struct phantom_nic_port *phantom_port,
uint32_t command, uint32_t arg1, uint32_t arg2,
uint32_t arg3 ) {
struct phantom_nic *phantom = phantom_port->phantom;
uint32_t signature;
int rc;
/* Issue command */
signature = NX_CDRP_SIGNATURE_MAKE ( phantom_port->port,
NXHAL_VERSION );
DBGC2 ( phantom, "Phantom %p port %d issuing command %08lx (%08lx, "
"%08lx, %08lx)\n", phantom, phantom_port->port,
command, arg1, arg2, arg3 );
phantom_writel ( phantom, signature, UNM_NIC_REG_NX_SIGN );
phantom_writel ( phantom, arg1, UNM_NIC_REG_NX_ARG1 );
phantom_writel ( phantom, arg2, UNM_NIC_REG_NX_ARG2 );
phantom_writel ( phantom, arg3, UNM_NIC_REG_NX_ARG3 );
phantom_writel ( phantom, NX_CDRP_FORM_CMD ( command ),
UNM_NIC_REG_NX_CDRP );
/* Wait for command to be accepted */
if ( ( rc = phantom_wait_for_cmd ( phantom ) ) != 0 ) {
DBGC ( phantom, "Phantom %p could not issue command: %s\n",
phantom, strerror ( rc ) );
return rc;
}
return 0;
}
/**
* Issue buffer-format command to firmware
*
* @v phantom_port Phantom NIC port
* @v command Firmware command
* @v buffer Buffer to pass to firmware
* @v len Length of buffer
* @ret rc Return status code
*/
static int phantom_issue_buf_cmd ( struct phantom_nic_port *phantom_port,
uint32_t command, void *buffer,
size_t len ) {
uint64_t physaddr;
physaddr = virt_to_bus ( buffer );
return phantom_issue_cmd ( phantom_port, command, ( physaddr >> 32 ),
( physaddr & 0xffffffffUL ), len );
}
/**
* Create Phantom RX context
*
* @v phantom_port Phantom NIC port
* @ret rc Return status code
*/
static int phantom_create_rx_ctx ( struct phantom_nic_port *phantom_port ) {
struct phantom_nic *phantom = phantom_port->phantom;
struct phantom_create_rx_ctx_rqrsp *buf;
int rc;
/* Prepare request */
buf = &phantom->dma_buf->create_rx_ctx;
memset ( buf, 0, sizeof ( *buf ) );
buf->hostrq.rx_ctx.host_rsp_dma_addr =
cpu_to_le64 ( virt_to_bus ( &buf->cardrsp ) );
buf->hostrq.rx_ctx.capabilities[0] =
cpu_to_le32 ( NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN );
buf->hostrq.rx_ctx.host_int_crb_mode =
cpu_to_le32 ( NX_HOST_INT_CRB_MODE_SHARED );
buf->hostrq.rx_ctx.host_rds_crb_mode =
cpu_to_le32 ( NX_HOST_RDS_CRB_MODE_UNIQUE );
buf->hostrq.rx_ctx.rds_ring_offset = cpu_to_le32 ( 0 );
buf->hostrq.rx_ctx.sds_ring_offset =
cpu_to_le32 ( sizeof ( buf->hostrq.rds ) );
buf->hostrq.rx_ctx.num_rds_rings = cpu_to_le16 ( 1 );
buf->hostrq.rx_ctx.num_sds_rings = cpu_to_le16 ( 1 );
buf->hostrq.rds.host_phys_addr =
cpu_to_le64 ( virt_to_bus ( phantom_port->desc->rds ) );
buf->hostrq.rds.buff_size = cpu_to_le64 ( PHN_RX_BUFSIZE );
buf->hostrq.rds.ring_size = cpu_to_le32 ( PHN_NUM_RDS );
buf->hostrq.rds.ring_kind = cpu_to_le32 ( NX_RDS_RING_TYPE_NORMAL );
buf->hostrq.sds.host_phys_addr =
cpu_to_le64 ( virt_to_bus ( phantom_port->desc->sds ) );
buf->hostrq.sds.ring_size = cpu_to_le32 ( PHN_NUM_SDS );
DBGC ( phantom, "Phantom %p port %d creating RX context\n",
phantom, phantom_port->port );
DBGC2_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
&buf->hostrq, sizeof ( buf->hostrq ) );
/* Issue request */
if ( ( rc = phantom_issue_buf_cmd ( phantom_port,
NX_CDRP_CMD_CREATE_RX_CTX,
&buf->hostrq,
sizeof ( buf->hostrq ) ) ) != 0 ) {
DBGC ( phantom, "Phantom %p port %d could not create RX "
"context: %s\n",
phantom, phantom_port->port, strerror ( rc ) );
DBGC ( phantom, "Request:\n" );
DBGC_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
&buf->hostrq, sizeof ( buf->hostrq ) );
DBGC ( phantom, "Response:\n" );
DBGC_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
&buf->cardrsp, sizeof ( buf->cardrsp ) );
return rc;
}
/* Retrieve context parameters */
phantom_port->rx_context_id =
le16_to_cpu ( buf->cardrsp.rx_ctx.context_id );
phantom_port->rds_producer_crb =
( UNM_CAM_RAM +
le32_to_cpu ( buf->cardrsp.rds.host_producer_crb ));
phantom_port->sds_consumer_crb =
( UNM_CAM_RAM +
le32_to_cpu ( buf->cardrsp.sds.host_consumer_crb ));
DBGC ( phantom, "Phantom %p port %d created RX context (id %04x, "
"port phys %02x virt %02x)\n", phantom, phantom_port->port,
phantom_port->rx_context_id, buf->cardrsp.rx_ctx.phys_port,
buf->cardrsp.rx_ctx.virt_port );
DBGC2_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
&buf->cardrsp, sizeof ( buf->cardrsp ) );
DBGC ( phantom, "Phantom %p port %d RDS producer CRB is %08lx\n",
phantom, phantom_port->port, phantom_port->rds_producer_crb );
DBGC ( phantom, "Phantom %p port %d SDS consumer CRB is %08lx\n",
phantom, phantom_port->port, phantom_port->sds_consumer_crb );
return 0;
}
/**
* Destroy Phantom RX context
*
* @v phantom_port Phantom NIC port
* @ret rc Return status code
*/
static void phantom_destroy_rx_ctx ( struct phantom_nic_port *phantom_port ) {
struct phantom_nic *phantom = phantom_port->phantom;
int rc;
DBGC ( phantom, "Phantom %p port %d destroying RX context (id %04x)\n",
phantom, phantom_port->port, phantom_port->rx_context_id );
/* Issue request */
if ( ( rc = phantom_issue_cmd ( phantom_port,
NX_CDRP_CMD_DESTROY_RX_CTX,
phantom_port->rx_context_id,
NX_DESTROY_CTX_RESET, 0 ) ) != 0 ) {
DBGC ( phantom, "Phantom %p port %d could not destroy RX "
"context: %s\n",
phantom, phantom_port->port, strerror ( rc ) );
/* We're probably screwed */
return;
}
/* Clear context parameters */
phantom_port->rx_context_id = 0;
phantom_port->rds_producer_crb = 0;
phantom_port->sds_consumer_crb = 0;
/* Reset software counters */
phantom_port->rds_producer_idx = 0;
phantom_port->rds_consumer_idx = 0;
phantom_port->sds_consumer_idx = 0;
}
/**
* Create Phantom TX context
*
* @v phantom_port Phantom NIC port
* @ret rc Return status code
*/
static int phantom_create_tx_ctx ( struct phantom_nic_port *phantom_port ) {
struct phantom_nic *phantom = phantom_port->phantom;
struct phantom_create_tx_ctx_rqrsp *buf;
int rc;
/* Prepare request */
buf = &phantom->dma_buf->create_tx_ctx;
memset ( buf, 0, sizeof ( *buf ) );
buf->hostrq.tx_ctx.host_rsp_dma_addr =
cpu_to_le64 ( virt_to_bus ( &buf->cardrsp ) );
buf->hostrq.tx_ctx.cmd_cons_dma_addr =
cpu_to_le64 ( virt_to_bus ( &phantom_port->desc->cmd_cons ) );
buf->hostrq.tx_ctx.dummy_dma_addr =
cpu_to_le64 ( virt_to_bus ( phantom->dma_buf->dummy_dma ) );
buf->hostrq.tx_ctx.capabilities[0] =
cpu_to_le32 ( NX_CAP0_LEGACY_CONTEXT | NX_CAP0_LEGACY_MN );
buf->hostrq.tx_ctx.host_int_crb_mode =
cpu_to_le32 ( NX_HOST_INT_CRB_MODE_SHARED );
buf->hostrq.tx_ctx.cds_ring.host_phys_addr =
cpu_to_le64 ( virt_to_bus ( phantom_port->desc->cds ) );
buf->hostrq.tx_ctx.cds_ring.ring_size = cpu_to_le32 ( PHN_NUM_CDS );
DBGC ( phantom, "Phantom %p port %d creating TX context\n",
phantom, phantom_port->port );
DBGC2_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
&buf->hostrq, sizeof ( buf->hostrq ) );
/* Issue request */
if ( ( rc = phantom_issue_buf_cmd ( phantom_port,
NX_CDRP_CMD_CREATE_TX_CTX,
&buf->hostrq,
sizeof ( buf->hostrq ) ) ) != 0 ) {
DBGC ( phantom, "Phantom %p port %d could not create TX "
"context: %s\n",
phantom, phantom_port->port, strerror ( rc ) );
DBGC ( phantom, "Request:\n" );
DBGC_HDA ( phantom, virt_to_bus ( &buf->hostrq ),
&buf->hostrq, sizeof ( buf->hostrq ) );
DBGC ( phantom, "Response:\n" );
DBGC_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
&buf->cardrsp, sizeof ( buf->cardrsp ) );
return rc;
}
/* Retrieve context parameters */
phantom_port->tx_context_id =
le16_to_cpu ( buf->cardrsp.tx_ctx.context_id );
phantom_port->cds_producer_crb =
( UNM_CAM_RAM +
le32_to_cpu(buf->cardrsp.tx_ctx.cds_ring.host_producer_crb));
DBGC ( phantom, "Phantom %p port %d created TX context (id %04x, "
"port phys %02x virt %02x)\n", phantom, phantom_port->port,
phantom_port->tx_context_id, buf->cardrsp.tx_ctx.phys_port,
buf->cardrsp.tx_ctx.virt_port );
DBGC2_HDA ( phantom, virt_to_bus ( &buf->cardrsp ),
&buf->cardrsp, sizeof ( buf->cardrsp ) );
DBGC ( phantom, "Phantom %p port %d CDS producer CRB is %08lx\n",
phantom, phantom_port->port, phantom_port->cds_producer_crb );
return 0;
}
/**
* Destroy Phantom TX context
*
* @v phantom_port Phantom NIC port
* @ret rc Return status code
*/
static void phantom_destroy_tx_ctx ( struct phantom_nic_port *phantom_port ) {
struct phantom_nic *phantom = phantom_port->phantom;
int rc;
DBGC ( phantom, "Phantom %p port %d destroying TX context (id %04x)\n",
phantom, phantom_port->port, phantom_port->tx_context_id );
/* Issue request */
if ( ( rc = phantom_issue_cmd ( phantom_port,
NX_CDRP_CMD_DESTROY_TX_CTX,
phantom_port->tx_context_id,
NX_DESTROY_CTX_RESET, 0 ) ) != 0 ) {
DBGC ( phantom, "Phantom %p port %d could not destroy TX "
"context: %s\n",
phantom, phantom_port->port, strerror ( rc ) );
/* We're probably screwed */
return;
}
/* Clear context parameters */
phantom_port->tx_context_id = 0;
phantom_port->cds_producer_crb = 0;
/* Reset software counters */
phantom_port->cds_producer_idx = 0;
phantom_port->cds_consumer_idx = 0;
}
/***************************************************************************
*
* Descriptor ring management
*
*/
/**
* Allocate Phantom RX descriptor
*
* @v phantom_port Phantom NIC port
* @ret index RX descriptor index, or negative error
*/
static int phantom_alloc_rds ( struct phantom_nic_port *phantom_port ) {
struct phantom_nic *phantom = phantom_port->phantom;
unsigned int rds_producer_idx;
unsigned int next_rds_producer_idx;