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intelxl.c
1692 lines (1448 loc) · 46.3 KB
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intelxl.c
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/*
* Copyright (C) 2018 Michael Brown <mbrown@fensystems.co.uk>.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
* You can also choose to distribute this program under the terms of
* the Unmodified Binary Distribution Licence (as given in the file
* COPYING.UBDL), provided that you have satisfied its requirements.
*/
FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
#include <stdint.h>
#include <string.h>
#include <stdio.h>
#include <unistd.h>
#include <errno.h>
#include <byteswap.h>
#include <ipxe/netdevice.h>
#include <ipxe/ethernet.h>
#include <ipxe/if_ether.h>
#include <ipxe/vlan.h>
#include <ipxe/iobuf.h>
#include <ipxe/malloc.h>
#include <ipxe/pci.h>
#include <ipxe/version.h>
#include "intelxl.h"
/** @file
*
* Intel 40 Gigabit Ethernet network card driver
*
*/
static void intelxl_reopen_admin ( struct intelxl_nic *intelxl );
/******************************************************************************
*
* Device reset
*
******************************************************************************
*/
/**
* Reset hardware
*
* @v intelxl Intel device
* @ret rc Return status code
*/
static int intelxl_reset ( struct intelxl_nic *intelxl ) {
uint32_t pfgen_ctrl;
/* Perform a global software reset */
pfgen_ctrl = readl ( intelxl->regs + INTELXL_PFGEN_CTRL );
writel ( ( pfgen_ctrl | INTELXL_PFGEN_CTRL_PFSWR ),
intelxl->regs + INTELXL_PFGEN_CTRL );
mdelay ( INTELXL_RESET_DELAY_MS );
return 0;
}
/******************************************************************************
*
* MAC address
*
******************************************************************************
*/
/**
* Fetch initial MAC address and maximum frame size
*
* @v intelxl Intel device
* @v netdev Network device
* @ret rc Return status code
*/
static int intelxl_fetch_mac ( struct intelxl_nic *intelxl,
struct net_device *netdev ) {
union intelxl_receive_address mac;
uint32_t prtgl_sal;
uint32_t prtgl_sah;
size_t mfs;
/* Read NVM-loaded address */
prtgl_sal = readl ( intelxl->regs + INTELXL_PRTGL_SAL );
prtgl_sah = readl ( intelxl->regs + INTELXL_PRTGL_SAH );
mac.reg.low = cpu_to_le32 ( prtgl_sal );
mac.reg.high = cpu_to_le32 ( prtgl_sah );
/* Check that address is valid */
if ( ! is_valid_ether_addr ( mac.raw ) ) {
DBGC ( intelxl, "INTELXL %p has invalid MAC address (%s)\n",
intelxl, eth_ntoa ( mac.raw ) );
return -ENOENT;
}
/* Copy MAC address */
DBGC ( intelxl, "INTELXL %p has autoloaded MAC address %s\n",
intelxl, eth_ntoa ( mac.raw ) );
memcpy ( netdev->hw_addr, mac.raw, ETH_ALEN );
/* Get maximum frame size */
mfs = INTELXL_PRTGL_SAH_MFS_GET ( prtgl_sah );
netdev->max_pkt_len = ( mfs - 4 /* CRC */ );
return 0;
}
/******************************************************************************
*
* Admin queue
*
******************************************************************************
*/
/** Admin queue register offsets */
static const struct intelxl_admin_offsets intelxl_admin_offsets = {
.bal = INTELXL_ADMIN_BAL,
.bah = INTELXL_ADMIN_BAH,
.len = INTELXL_ADMIN_LEN,
.head = INTELXL_ADMIN_HEAD,
.tail = INTELXL_ADMIN_TAIL,
};
/**
* Allocate admin queue
*
* @v intelxl Intel device
* @v admin Admin queue
* @ret rc Return status code
*/
static int intelxl_alloc_admin ( struct intelxl_nic *intelxl,
struct intelxl_admin *admin ) {
size_t buf_len = ( sizeof ( admin->buf[0] ) * INTELXL_ADMIN_NUM_DESC );
size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
/* Allocate admin queue */
admin->buf = malloc_dma ( ( buf_len + len ), INTELXL_ALIGN );
if ( ! admin->buf )
return -ENOMEM;
admin->desc = ( ( ( void * ) admin->buf ) + buf_len );
DBGC ( intelxl, "INTELXL %p A%cQ is at [%08llx,%08llx) buf "
"[%08llx,%08llx)\n", intelxl,
( ( admin == &intelxl->command ) ? 'T' : 'R' ),
( ( unsigned long long ) virt_to_bus ( admin->desc ) ),
( ( unsigned long long ) ( virt_to_bus ( admin->desc ) + len ) ),
( ( unsigned long long ) virt_to_bus ( admin->buf ) ),
( ( unsigned long long ) ( virt_to_bus ( admin->buf ) +
buf_len ) ) );
return 0;
}
/**
* Enable admin queue
*
* @v intelxl Intel device
* @v admin Admin queue
*/
static void intelxl_enable_admin ( struct intelxl_nic *intelxl,
struct intelxl_admin *admin ) {
size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
const struct intelxl_admin_offsets *regs = admin->regs;
void *admin_regs = ( intelxl->regs + admin->base );
physaddr_t address;
/* Initialise admin queue */
memset ( admin->desc, 0, len );
/* Reset head and tail registers */
writel ( 0, admin_regs + regs->head );
writel ( 0, admin_regs + regs->tail );
/* Reset queue index */
admin->index = 0;
/* Program queue address */
address = virt_to_bus ( admin->desc );
writel ( ( address & 0xffffffffUL ), admin_regs + regs->bal );
if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
writel ( ( ( ( uint64_t ) address ) >> 32 ),
admin_regs + regs->bah );
} else {
writel ( 0, admin_regs + regs->bah );
}
/* Program queue length and enable queue */
writel ( ( INTELXL_ADMIN_LEN_LEN ( INTELXL_ADMIN_NUM_DESC ) |
INTELXL_ADMIN_LEN_ENABLE ),
admin_regs + regs->len );
}
/**
* Disable admin queue
*
* @v intelxl Intel device
* @v admin Admin queue
*/
static void intelxl_disable_admin ( struct intelxl_nic *intelxl,
struct intelxl_admin *admin ) {
const struct intelxl_admin_offsets *regs = admin->regs;
void *admin_regs = ( intelxl->regs + admin->base );
/* Disable queue */
writel ( 0, admin_regs + regs->len );
}
/**
* Free admin queue
*
* @v intelxl Intel device
* @v admin Admin queue
*/
static void intelxl_free_admin ( struct intelxl_nic *intelxl __unused,
struct intelxl_admin *admin ) {
size_t buf_len = ( sizeof ( admin->buf[0] ) * INTELXL_ADMIN_NUM_DESC );
size_t len = ( sizeof ( admin->desc[0] ) * INTELXL_ADMIN_NUM_DESC );
/* Free queue */
free_dma ( admin->buf, ( buf_len + len ) );
}
/**
* Get next admin command queue descriptor
*
* @v intelxl Intel device
* @ret cmd Command descriptor
*/
static struct intelxl_admin_descriptor *
intelxl_admin_command_descriptor ( struct intelxl_nic *intelxl ) {
struct intelxl_admin *admin = &intelxl->command;
struct intelxl_admin_descriptor *cmd;
/* Get and initialise next descriptor */
cmd = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
memset ( cmd, 0, sizeof ( *cmd ) );
return cmd;
}
/**
* Get next admin command queue data buffer
*
* @v intelxl Intel device
* @ret buf Data buffer
*/
static union intelxl_admin_buffer *
intelxl_admin_command_buffer ( struct intelxl_nic *intelxl ) {
struct intelxl_admin *admin = &intelxl->command;
union intelxl_admin_buffer *buf;
/* Get next data buffer */
buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
memset ( buf, 0, sizeof ( *buf ) );
return buf;
}
/**
* Initialise admin event queue descriptor
*
* @v intelxl Intel device
* @v index Event queue index
*/
static void intelxl_admin_event_init ( struct intelxl_nic *intelxl,
unsigned int index ) {
struct intelxl_admin *admin = &intelxl->event;
struct intelxl_admin_descriptor *evt;
union intelxl_admin_buffer *buf;
uint64_t address;
/* Initialise descriptor */
evt = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
address = virt_to_bus ( buf );
evt->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
evt->len = cpu_to_le16 ( sizeof ( *buf ) );
evt->params.buffer.high = cpu_to_le32 ( address >> 32 );
evt->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
}
/**
* Issue admin queue command
*
* @v intelxl Intel device
* @ret rc Return status code
*/
static int intelxl_admin_command ( struct intelxl_nic *intelxl ) {
struct intelxl_admin *admin = &intelxl->command;
const struct intelxl_admin_offsets *regs = admin->regs;
void *admin_regs = ( intelxl->regs + admin->base );
struct intelxl_admin_descriptor *cmd;
union intelxl_admin_buffer *buf;
uint64_t address;
uint32_t cookie;
unsigned int index;
unsigned int tail;
unsigned int i;
int rc;
/* Get next queue entry */
index = admin->index++;
tail = ( admin->index % INTELXL_ADMIN_NUM_DESC );
cmd = &admin->desc[ index % INTELXL_ADMIN_NUM_DESC ];
buf = &admin->buf[ index % INTELXL_ADMIN_NUM_DESC ];
DBGC2 ( intelxl, "INTELXL %p admin command %#x opcode %#04x",
intelxl, index, le16_to_cpu ( cmd->opcode ) );
if ( cmd->vopcode )
DBGC2 ( intelxl, "/%#08x", le32_to_cpu ( cmd->vopcode ) );
DBGC2 ( intelxl, ":\n" );
/* Sanity checks */
assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_DD ) ) );
assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_CMP ) ) );
assert ( ! ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_ERR ) ) );
assert ( cmd->ret == 0 );
/* Populate data buffer address if applicable */
if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
address = virt_to_bus ( buf );
cmd->params.buffer.high = cpu_to_le32 ( address >> 32 );
cmd->params.buffer.low = cpu_to_le32 ( address & 0xffffffffUL );
}
/* Populate cookie, if not being (ab)used for VF opcode */
if ( ! cmd->vopcode )
cmd->cookie = cpu_to_le32 ( index );
/* Record cookie */
cookie = cmd->cookie;
/* Post command descriptor */
DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
if ( cmd->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
le16_to_cpu ( cmd->len ) );
}
wmb();
writel ( tail, admin_regs + regs->tail );
/* Wait for completion */
for ( i = 0 ; i < INTELXL_ADMIN_MAX_WAIT_MS ; i++ ) {
/* If response is not complete, delay 1ms and retry */
if ( ! ( cmd->flags & INTELXL_ADMIN_FL_DD ) ) {
mdelay ( 1 );
continue;
}
DBGC2 ( intelxl, "INTELXL %p admin command %#x response:\n",
intelxl, index );
DBGC2_HDA ( intelxl, virt_to_phys ( cmd ), cmd,
sizeof ( *cmd ) );
/* Check for cookie mismatch */
if ( cmd->cookie != cookie ) {
DBGC ( intelxl, "INTELXL %p admin command %#x bad "
"cookie %#x\n", intelxl, index,
le32_to_cpu ( cmd->cookie ) );
rc = -EPROTO;
goto err;
}
/* Check for errors */
if ( cmd->ret != 0 ) {
DBGC ( intelxl, "INTELXL %p admin command %#x error "
"%d\n", intelxl, index,
le16_to_cpu ( cmd->ret ) );
rc = -EIO;
goto err;
}
/* Success */
return 0;
}
rc = -ETIMEDOUT;
DBGC ( intelxl, "INTELXL %p timed out waiting for admin command %#x:\n",
intelxl, index );
err:
DBGC_HDA ( intelxl, virt_to_phys ( cmd ), cmd, sizeof ( *cmd ) );
return rc;
}
/**
* Get firmware version
*
* @v intelxl Intel device
* @ret rc Return status code
*/
static int intelxl_admin_version ( struct intelxl_nic *intelxl ) {
struct intelxl_admin_descriptor *cmd;
struct intelxl_admin_version_params *version;
unsigned int api;
int rc;
/* Populate descriptor */
cmd = intelxl_admin_command_descriptor ( intelxl );
cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_VERSION );
version = &cmd->params.version;
/* Issue command */
if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
return rc;
api = le16_to_cpu ( version->api.major );
DBGC ( intelxl, "INTELXL %p firmware v%d.%d API v%d.%d\n",
intelxl, le16_to_cpu ( version->firmware.major ),
le16_to_cpu ( version->firmware.minor ),
api, le16_to_cpu ( version->api.minor ) );
/* Check for API compatibility */
if ( api > INTELXL_ADMIN_API_MAJOR ) {
DBGC ( intelxl, "INTELXL %p unsupported API v%d\n",
intelxl, api );
return -ENOTSUP;
}
return 0;
}
/**
* Report driver version
*
* @v intelxl Intel device
* @ret rc Return status code
*/
static int intelxl_admin_driver ( struct intelxl_nic *intelxl ) {
struct intelxl_admin_descriptor *cmd;
struct intelxl_admin_driver_params *driver;
union intelxl_admin_buffer *buf;
int rc;
/* Populate descriptor */
cmd = intelxl_admin_command_descriptor ( intelxl );
cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_DRIVER );
cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_RD | INTELXL_ADMIN_FL_BUF );
cmd->len = cpu_to_le16 ( sizeof ( buf->driver ) );
driver = &cmd->params.driver;
driver->major = product_major_version;
driver->minor = product_minor_version;
buf = intelxl_admin_command_buffer ( intelxl );
snprintf ( buf->driver.name, sizeof ( buf->driver.name ), "%s",
( product_name[0] ? product_name : product_short_name ) );
/* Issue command */
if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
return rc;
return 0;
}
/**
* Shutdown admin queues
*
* @v intelxl Intel device
* @ret rc Return status code
*/
static int intelxl_admin_shutdown ( struct intelxl_nic *intelxl ) {
struct intelxl_admin_descriptor *cmd;
struct intelxl_admin_shutdown_params *shutdown;
int rc;
/* Populate descriptor */
cmd = intelxl_admin_command_descriptor ( intelxl );
cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_SHUTDOWN );
shutdown = &cmd->params.shutdown;
shutdown->unloading = INTELXL_ADMIN_SHUTDOWN_UNLOADING;
/* Issue command */
if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
return rc;
return 0;
}
/**
* Get switch configuration
*
* @v intelxl Intel device
* @ret rc Return status code
*/
static int intelxl_admin_switch ( struct intelxl_nic *intelxl ) {
struct intelxl_admin_descriptor *cmd;
struct intelxl_admin_switch_params *sw;
union intelxl_admin_buffer *buf;
int rc;
/* Populate descriptor */
cmd = intelxl_admin_command_descriptor ( intelxl );
cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_SWITCH );
cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
cmd->len = cpu_to_le16 ( sizeof ( buf->sw ) );
sw = &cmd->params.sw;
buf = intelxl_admin_command_buffer ( intelxl );
/* Get each configuration in turn */
do {
/* Issue command */
if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
return rc;
/* Dump raw configuration */
DBGC2 ( intelxl, "INTELXL %p SEID %#04x:\n",
intelxl, le16_to_cpu ( buf->sw.cfg.seid ) );
DBGC2_HDA ( intelxl, 0, &buf->sw.cfg, sizeof ( buf->sw.cfg ) );
/* Parse response */
if ( buf->sw.cfg.type == INTELXL_ADMIN_SWITCH_TYPE_VSI ) {
intelxl->vsi = le16_to_cpu ( buf->sw.cfg.seid );
DBGC ( intelxl, "INTELXL %p VSI %#04x uplink %#04x "
"downlink %#04x conn %#02x\n", intelxl,
intelxl->vsi, le16_to_cpu ( buf->sw.cfg.uplink ),
le16_to_cpu ( buf->sw.cfg.downlink ),
buf->sw.cfg.connection );
}
} while ( sw->next );
/* Check that we found a VSI */
if ( ! intelxl->vsi ) {
DBGC ( intelxl, "INTELXL %p has no VSI\n", intelxl );
return -ENOENT;
}
return 0;
}
/**
* Get VSI parameters
*
* @v intelxl Intel device
* @ret rc Return status code
*/
static int intelxl_admin_vsi ( struct intelxl_nic *intelxl ) {
struct intelxl_admin_descriptor *cmd;
struct intelxl_admin_vsi_params *vsi;
union intelxl_admin_buffer *buf;
int rc;
/* Populate descriptor */
cmd = intelxl_admin_command_descriptor ( intelxl );
cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_VSI );
cmd->flags = cpu_to_le16 ( INTELXL_ADMIN_FL_BUF );
cmd->len = cpu_to_le16 ( sizeof ( buf->vsi ) );
vsi = &cmd->params.vsi;
vsi->vsi = cpu_to_le16 ( intelxl->vsi );
buf = intelxl_admin_command_buffer ( intelxl );
/* Issue command */
if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
return rc;
/* Parse response */
intelxl->queue = le16_to_cpu ( buf->vsi.queue[0] );
intelxl->qset = le16_to_cpu ( buf->vsi.qset[0] );
DBGC ( intelxl, "INTELXL %p VSI %#04x queue %#04x qset %#04x\n",
intelxl, intelxl->vsi, intelxl->queue, intelxl->qset );
return 0;
}
/**
* Set VSI promiscuous modes
*
* @v intelxl Intel device
* @ret rc Return status code
*/
static int intelxl_admin_promisc ( struct intelxl_nic *intelxl ) {
struct intelxl_admin_descriptor *cmd;
struct intelxl_admin_promisc_params *promisc;
uint16_t flags;
int rc;
/* Populate descriptor */
cmd = intelxl_admin_command_descriptor ( intelxl );
cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_PROMISC );
flags = ( INTELXL_ADMIN_PROMISC_FL_UNICAST |
INTELXL_ADMIN_PROMISC_FL_MULTICAST |
INTELXL_ADMIN_PROMISC_FL_BROADCAST |
INTELXL_ADMIN_PROMISC_FL_VLAN );
promisc = &cmd->params.promisc;
promisc->flags = cpu_to_le16 ( flags );
promisc->valid = cpu_to_le16 ( flags );
promisc->vsi = cpu_to_le16 ( intelxl->vsi );
/* Issue command */
if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
return rc;
return 0;
}
/**
* Restart autonegotiation
*
* @v intelxl Intel device
* @ret rc Return status code
*/
static int intelxl_admin_autoneg ( struct intelxl_nic *intelxl ) {
struct intelxl_admin_descriptor *cmd;
struct intelxl_admin_autoneg_params *autoneg;
int rc;
/* Populate descriptor */
cmd = intelxl_admin_command_descriptor ( intelxl );
cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_AUTONEG );
autoneg = &cmd->params.autoneg;
autoneg->flags = ( INTELXL_ADMIN_AUTONEG_FL_RESTART |
INTELXL_ADMIN_AUTONEG_FL_ENABLE );
/* Issue command */
if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
return rc;
return 0;
}
/**
* Get link status
*
* @v netdev Network device
* @ret rc Return status code
*/
static int intelxl_admin_link ( struct net_device *netdev ) {
struct intelxl_nic *intelxl = netdev->priv;
struct intelxl_admin_descriptor *cmd;
struct intelxl_admin_link_params *link;
int rc;
/* Populate descriptor */
cmd = intelxl_admin_command_descriptor ( intelxl );
cmd->opcode = cpu_to_le16 ( INTELXL_ADMIN_LINK );
link = &cmd->params.link;
link->notify = INTELXL_ADMIN_LINK_NOTIFY;
/* Issue command */
if ( ( rc = intelxl_admin_command ( intelxl ) ) != 0 )
return rc;
DBGC ( intelxl, "INTELXL %p PHY %#02x speed %#02x status %#02x\n",
intelxl, link->phy, link->speed, link->status );
/* Update network device */
if ( link->status & INTELXL_ADMIN_LINK_UP ) {
netdev_link_up ( netdev );
} else {
netdev_link_down ( netdev );
}
return 0;
}
/**
* Handle virtual function event (when VF driver is not present)
*
* @v netdev Network device
* @v evt Admin queue event descriptor
* @v buf Admin queue event data buffer
*/
__weak void
intelxlvf_admin_event ( struct net_device *netdev __unused,
struct intelxl_admin_descriptor *evt __unused,
union intelxl_admin_buffer *buf __unused ) {
/* Nothing to do */
}
/**
* Refill admin event queue
*
* @v intelxl Intel device
*/
static void intelxl_refill_admin ( struct intelxl_nic *intelxl ) {
struct intelxl_admin *admin = &intelxl->event;
const struct intelxl_admin_offsets *regs = admin->regs;
void *admin_regs = ( intelxl->regs + admin->base );
unsigned int tail;
/* Update tail pointer */
tail = ( ( admin->index + INTELXL_ADMIN_NUM_DESC - 1 ) %
INTELXL_ADMIN_NUM_DESC );
wmb();
writel ( tail, admin_regs + regs->tail );
}
/**
* Poll admin event queue
*
* @v netdev Network device
*/
static void intelxl_poll_admin ( struct net_device *netdev ) {
struct intelxl_nic *intelxl = netdev->priv;
struct intelxl_admin *admin = &intelxl->event;
struct intelxl_admin_descriptor *evt;
union intelxl_admin_buffer *buf;
/* Check for events */
while ( 1 ) {
/* Get next event descriptor and data buffer */
evt = &admin->desc[ admin->index % INTELXL_ADMIN_NUM_DESC ];
buf = &admin->buf[ admin->index % INTELXL_ADMIN_NUM_DESC ];
/* Stop if descriptor is not yet completed */
if ( ! ( evt->flags & INTELXL_ADMIN_FL_DD ) )
return;
DBGC2 ( intelxl, "INTELXL %p admin event %#x:\n",
intelxl, admin->index );
DBGC2_HDA ( intelxl, virt_to_phys ( evt ), evt,
sizeof ( *evt ) );
if ( evt->flags & cpu_to_le16 ( INTELXL_ADMIN_FL_BUF ) ) {
DBGC2_HDA ( intelxl, virt_to_phys ( buf ), buf,
le16_to_cpu ( evt->len ) );
}
/* Handle event */
switch ( evt->opcode ) {
case cpu_to_le16 ( INTELXL_ADMIN_LINK ):
intelxl_admin_link ( netdev );
break;
case cpu_to_le16 ( INTELXL_ADMIN_SEND_TO_VF ):
intelxlvf_admin_event ( netdev, evt, buf );
break;
default:
DBGC ( intelxl, "INTELXL %p admin event %#x "
"unrecognised opcode %#04x\n", intelxl,
admin->index, le16_to_cpu ( evt->opcode ) );
break;
}
/* Reset descriptor and refill queue */
intelxl_admin_event_init ( intelxl, admin->index );
admin->index++;
intelxl_refill_admin ( intelxl );
}
}
/**
* Open admin queues
*
* @v intelxl Intel device
* @ret rc Return status code
*/
static int intelxl_open_admin ( struct intelxl_nic *intelxl ) {
int rc;
/* Allocate admin event queue */
if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->event ) ) != 0 )
goto err_alloc_event;
/* Allocate admin command queue */
if ( ( rc = intelxl_alloc_admin ( intelxl, &intelxl->command ) ) != 0 )
goto err_alloc_command;
/* (Re)open admin queues */
intelxl_reopen_admin ( intelxl );
/* Get firmware version */
if ( ( rc = intelxl_admin_version ( intelxl ) ) != 0 )
goto err_version;
/* Report driver version */
if ( ( rc = intelxl_admin_driver ( intelxl ) ) != 0 )
goto err_driver;
return 0;
err_driver:
err_version:
intelxl_disable_admin ( intelxl, &intelxl->command );
intelxl_disable_admin ( intelxl, &intelxl->event );
intelxl_free_admin ( intelxl, &intelxl->command );
err_alloc_command:
intelxl_free_admin ( intelxl, &intelxl->event );
err_alloc_event:
return rc;
}
/**
* Reopen admin queues (after virtual function reset)
*
* @v intelxl Intel device
*/
static void intelxl_reopen_admin ( struct intelxl_nic *intelxl ) {
unsigned int i;
/* Enable admin event queue */
intelxl_enable_admin ( intelxl, &intelxl->event );
/* Enable admin command queue */
intelxl_enable_admin ( intelxl, &intelxl->command );
/* Initialise all admin event queue descriptors */
for ( i = 0 ; i < INTELXL_ADMIN_NUM_DESC ; i++ )
intelxl_admin_event_init ( intelxl, i );
/* Post all descriptors to event queue */
intelxl_refill_admin ( intelxl );
}
/**
* Close admin queues
*
* @v intelxl Intel device
*/
static void intelxl_close_admin ( struct intelxl_nic *intelxl ) {
/* Shut down admin queues */
intelxl_admin_shutdown ( intelxl );
/* Disable admin queues */
intelxl_disable_admin ( intelxl, &intelxl->command );
intelxl_disable_admin ( intelxl, &intelxl->event );
/* Free admin queues */
intelxl_free_admin ( intelxl, &intelxl->command );
intelxl_free_admin ( intelxl, &intelxl->event );
}
/******************************************************************************
*
* Descriptor rings
*
******************************************************************************
*/
/**
* Dump queue context (for debugging)
*
* @v intelxl Intel device
* @v op Context operation
* @v len Size of context
*/
static __attribute__ (( unused )) void
intelxl_context_dump ( struct intelxl_nic *intelxl, uint32_t op, size_t len ) {
struct intelxl_context_line line;
uint32_t pfcm_lanctxctl;
uint32_t pfcm_lanctxstat;
unsigned int queue;
unsigned int index;
unsigned int i;
/* Do nothing unless debug output is enabled */
if ( ! DBG_EXTRA )
return;
/* Dump context */
DBGC2 ( intelxl, "INTELXL %p context %#08x:\n", intelxl, op );
for ( index = 0 ; ( sizeof ( line ) * index ) < len ; index++ ) {
/* Start context operation */
queue = ( intelxl->base + intelxl->queue );
pfcm_lanctxctl =
( INTELXL_PFCM_LANCTXCTL_QUEUE_NUM ( queue ) |
INTELXL_PFCM_LANCTXCTL_SUB_LINE ( index ) |
INTELXL_PFCM_LANCTXCTL_OP_CODE_READ | op );
writel ( pfcm_lanctxctl,
intelxl->regs + INTELXL_PFCM_LANCTXCTL );
/* Wait for operation to complete */
for ( i = 0 ; i < INTELXL_CTX_MAX_WAIT_MS ; i++ ) {
/* Check if operation is complete */
pfcm_lanctxstat = readl ( intelxl->regs +
INTELXL_PFCM_LANCTXSTAT );
if ( pfcm_lanctxstat & INTELXL_PFCM_LANCTXSTAT_DONE )
break;
/* Delay */
mdelay ( 1 );
}
/* Read context data */
for ( i = 0 ; i < ( sizeof ( line ) /
sizeof ( line.raw[0] ) ) ; i++ ) {
line.raw[i] = readl ( intelxl->regs +
INTELXL_PFCM_LANCTXDATA ( i ) );
}
DBGC2_HDA ( intelxl, ( sizeof ( line ) * index ),
&line, sizeof ( line ) );
}
}
/**
* Program queue context line
*
* @v intelxl Intel device
* @v line Queue context line
* @v index Line number
* @v op Context operation
* @ret rc Return status code
*/
static int intelxl_context_line ( struct intelxl_nic *intelxl,
struct intelxl_context_line *line,
unsigned int index, uint32_t op ) {
uint32_t pfcm_lanctxctl;
uint32_t pfcm_lanctxstat;
unsigned int queue;
unsigned int i;
/* Write context data */
for ( i = 0; i < ( sizeof ( *line ) / sizeof ( line->raw[0] ) ); i++ ) {
writel ( le32_to_cpu ( line->raw[i] ),
intelxl->regs + INTELXL_PFCM_LANCTXDATA ( i ) );
}
/* Start context operation */
queue = ( intelxl->base + intelxl->queue );
pfcm_lanctxctl = ( INTELXL_PFCM_LANCTXCTL_QUEUE_NUM ( queue ) |
INTELXL_PFCM_LANCTXCTL_SUB_LINE ( index ) |
INTELXL_PFCM_LANCTXCTL_OP_CODE_WRITE | op );
writel ( pfcm_lanctxctl, intelxl->regs + INTELXL_PFCM_LANCTXCTL );
/* Wait for operation to complete */
for ( i = 0 ; i < INTELXL_CTX_MAX_WAIT_MS ; i++ ) {
/* Check if operation is complete */
pfcm_lanctxstat = readl ( intelxl->regs +
INTELXL_PFCM_LANCTXSTAT );
if ( pfcm_lanctxstat & INTELXL_PFCM_LANCTXSTAT_DONE )
return 0;
/* Delay */
mdelay ( 1 );
}
DBGC ( intelxl, "INTELXL %p timed out waiting for context: %#08x\n",
intelxl, pfcm_lanctxctl );
return -ETIMEDOUT;
}
/**
* Program queue context
*
* @v intelxl Intel device
* @v line Queue context lines
* @v len Size of context
* @v op Context operation
* @ret rc Return status code
*/
static int intelxl_context ( struct intelxl_nic *intelxl,
struct intelxl_context_line *line,
size_t len, uint32_t op ) {
unsigned int index;
int rc;
DBGC2 ( intelxl, "INTELXL %p context %#08x len %#zx:\n",
intelxl, op, len );
DBGC2_HDA ( intelxl, 0, line, len );
/* Program one line at a time */
for ( index = 0 ; ( sizeof ( *line ) * index ) < len ; index++ ) {
if ( ( rc = intelxl_context_line ( intelxl, line++, index,
op ) ) != 0 )
return rc;
}
return 0;
}
/**
* Program transmit queue context
*
* @v intelxl Intel device
* @v address Descriptor ring base address
* @ret rc Return status code
*/
static int intelxl_context_tx ( struct intelxl_nic *intelxl,
physaddr_t address ) {
union {
struct intelxl_context_tx tx;
struct intelxl_context_line line;
} ctx;
int rc;
/* Initialise context */
memset ( &ctx, 0, sizeof ( ctx ) );
ctx.tx.flags = cpu_to_le16 ( INTELXL_CTX_TX_FL_NEW );
ctx.tx.base = cpu_to_le64 ( INTELXL_CTX_TX_BASE ( address ) );
ctx.tx.count =
cpu_to_le16 ( INTELXL_CTX_TX_COUNT ( INTELXL_TX_NUM_DESC ) );
ctx.tx.qset = INTELXL_CTX_TX_QSET ( intelxl->qset );
/* Program context */
if ( ( rc = intelxl_context ( intelxl, &ctx.line, sizeof ( ctx ),
INTELXL_PFCM_LANCTXCTL_TYPE_TX ) ) != 0 )
return rc;
return 0;
}
/**