[tg3] Add support for SerDes PHY initialization

Signed-off-by: Michael Brown <mcb30@ipxe.org>

src/drivers/net/tg3/tg3.h

@@ -34,6 +34,13 @@
 #define ADVERTISED_Autoneg              (1 << 6)
 /* </ethtool.h> */
 
+#ifndef ADVERTISED_Pause
+#define ADVERTISED_Pause                (1 << 13)
+#endif
+#ifndef ADVERTISED_Asym_Pause
+#define ADVERTISED_Asym_Pause           (1 << 14)
+#endif
+
 /* mdio.h: */
 #define MDIO_AN_EEE_ADV		60      /* EEE advertisement */
 
@@ -139,9 +146,15 @@
 #define SPEED_10			10
 #define SPEED_100			100
 #define SPEED_1000			1000
+#ifndef SPEED_UNKNOWN
+#define SPEED_UNKNOWN                   -1
+#endif
 
 #define DUPLEX_HALF			0x00
 #define DUPLEX_FULL			0x01
+#ifndef DUPLEX_UNKNOWN
+#define DUPLEX_UNKNOWN                  0xff
+#endif
 
 #define TG3_64BIT_REG_HIGH		0x00UL
 #define TG3_64BIT_REG_LOW		0x04UL
@@ -2425,6 +2438,14 @@
 #define MII_TG3_FET_SHDW_AUXSTAT2	0x1b
 #define  MII_TG3_FET_SHDW_AUXSTAT2_APD	0x0020
 
+/* Serdes PHY Register Definitions */
+#define SERDES_TG3_1000X_STATUS         0x14
+#define SERDES_TG3_SGMII_MODE           0x0001
+#define SERDES_TG3_LINK_UP              0x0002
+#define SERDES_TG3_FULL_DUPLEX          0x0004
+#define SERDES_TG3_SPEED_100            0x0008
+#define SERDES_TG3_SPEED_1000           0x0010
+
 
 /* APE registers.  Accessible through BAR1 */
 #define TG3_APE_EVENT			0x000c
@@ -2815,6 +2836,7 @@ struct tg3_link_config {
 #define DUPLEX_INVALID		0xff
 #define AUTONEG_INVALID		0xff
 	u16				active_speed;
+	u32				rmt_adv;
 
 	/* When we go in and out of low power mode we need
 	 * to swap with this state.
@@ -3282,6 +3304,7 @@ struct tg3 {
 
 	u16				subsystem_vendor;
 	u16				subsystem_device;
+	int				link_up;
 };
 
 #define TG3_TX_RING_SIZE		512
@@ -3410,6 +3433,39 @@ static inline u8 mii_resolve_flowctrl_fdx(u16 lcladv, u16 rmtadv)
 	return cap;
 }
 
+static inline u32 mii_adv_to_ethtool_adv_x(u32 adv)
+{
+	u32 result = 0;
+
+	if (adv & ADVERTISE_1000XHALF)
+		result |= ADVERTISED_1000baseT_Half;
+	if (adv & ADVERTISE_1000XFULL)
+		result |= ADVERTISED_1000baseT_Full;
+	if (adv & ADVERTISE_1000XPAUSE)
+		result |= ADVERTISED_Pause;
+	if (adv & ADVERTISE_1000XPSE_ASYM)
+		result |= ADVERTISED_Asym_Pause;
+
+	return result;
+}
+
+static inline u32 ethtool_adv_to_mii_adv_x(u32 ethadv)
+{
+	u32 result = 0;
+
+	if (ethadv & ADVERTISED_1000baseT_Half)
+		result |= ADVERTISE_1000XHALF;
+	if (ethadv & ADVERTISED_1000baseT_Full)
+		result |= ADVERTISE_1000XFULL;
+	if (ethadv & ADVERTISED_Pause)
+		result |= ADVERTISE_1000XPAUSE;
+	if (ethadv & ADVERTISED_Asym_Pause)
+		result |= ADVERTISE_1000XPSE_ASYM;
+
+	return result;
+}
+
+
 #define ETH_FCS_LEN 4
 
 #endif /* !(_T3_H) */