iPXE - Open Source Boot Firmware

[ath5k] Save proper cacheline size when fixing PCI configuration
authorJoshua Oreman <oremanj@rwcr.net>
Fri, 16 Oct 2009 23:27:43 +0000 (19:27 -0400)
committerMarty Connor <mdc@etherboot.org>
Sat, 17 Oct 2009 00:25:17 +0000 (20:25 -0400)
commit7296f1f21c442e0781e7c3efe1f1a1005cf3e385
treed10b9854d8a7a41c6f23ddb965284d2e78ab64a9
parent489bd2f396e62e2ec1139da93e242017a7f6e9f5
[ath5k] Save proper cacheline size when fixing PCI configuration

Some BIOSes set the PCI cacheline size to zero for the card; the ath5k
driver fixes it to a reasonable in PCI config space, but failed to
correct the internal value it had already read. This resulted in
divide-by-zero errors when cacheline-aligning various data structures.

Fix by setting the internal cachelsz to a sane value at the same time
as we write that value to PCI config space.

Signed-off-by: Marty Connor <mdc@etherboot.org>
src/drivers/net/ath5k/ath5k.c