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small speedups
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sshwarts committed Nov 7, 2007
1 parent 426c42e commit 315e5ad
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Showing 5 changed files with 53 additions and 60 deletions.
38 changes: 25 additions & 13 deletions cpu/cpu.h
@@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.346 2007/11/05 16:28:02 sshwarts Exp $
// $Id: cpu.h,v 1.347 2007/11/07 10:40:39 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
Expand Down Expand Up @@ -638,12 +638,14 @@ class bxInstruction_c {
// in the accessor.
// 27..20 modRM (modrm)
// 19..16 index (sib)
// 15..12 base (sib)
// 11...8 nnn (modrm)
Bit16u modRMData2;

// 15..12 nnn (modrm)
// 11...8 base (sib)
// 7...6 mod (modrm)
// 5...4 scale (sib)
// 3...0 rm (modrm)
Bit32u modRMData;
Bit16u modRMData1;

union {
Bit32u Id;
Expand Down Expand Up @@ -699,27 +701,31 @@ class bxInstruction_c {
// are aligned in the same place, so it doesn't matter.
return IxForm.opcodeReg;
}
BX_CPP_INLINE unsigned modrm() { return (modRMForm.modRMData>>20) & 0xff; }
BX_CPP_INLINE unsigned mod() { return modRMForm.modRMData & 0xc0; }
BX_CPP_INLINE unsigned modrm() { return (modRMForm.modRMData2>>4) & 0xff; }
BX_CPP_INLINE unsigned mod() { return modRMForm.modRMData1 & 0xc0; }
BX_CPP_INLINE unsigned modC0()
{
// This is a cheaper way to test for modRM instructions where
// the mod field is 0xc0. FetchDecode flags this condition since
// it is quite common to be tested for.
return metaInfo & (1<<22);
}
BX_CPP_INLINE unsigned assertModC0()
{
return metaInfo |= (1<<22);
}
BX_CPP_INLINE unsigned nnn() {
return (modRMForm.modRMData >> 8) & 0xf;
return (modRMForm.modRMData1 >> 12);
}
BX_CPP_INLINE unsigned rm() { return modRMForm.modRMData & 0xf; }
BX_CPP_INLINE unsigned rm() { return modRMForm.modRMData1 & 0xf; }
BX_CPP_INLINE unsigned sibScale() {
return (modRMForm.modRMData >> 4) & 0x3;
return (modRMForm.modRMData1 >> 4) & 0x3;
}
BX_CPP_INLINE unsigned sibIndex() {
return (modRMForm.modRMData >> 16) & 0xf;
return (modRMForm.modRMData2) & 0xf;
}
BX_CPP_INLINE unsigned sibBase() {
return (modRMForm.modRMData >> 12) & 0xf;
return (modRMForm.modRMData1 >> 8) & 0xf;
}
BX_CPP_INLINE Bit32u displ32u() { return modRMForm.displ32u; }
BX_CPP_INLINE Bit16u displ16u() { return modRMForm.displ16u; }
Expand Down Expand Up @@ -2939,8 +2945,14 @@ class BOCHSAPI BX_CPU_C : public logfunctions {
unsigned rw, void *data) BX_CPP_AttrRegparmN(3);
BX_SMF void page_fault(unsigned fault, bx_address laddr, unsigned pl, unsigned rw, unsigned access_type);
BX_SMF bx_phy_address translate_linear(bx_address laddr, unsigned pl, unsigned rw, unsigned access_type);
BX_SMF bx_phy_address itranslate_linear(bx_address laddr, unsigned pl) BX_CPP_AttrRegparmN(2);
BX_SMF bx_phy_address dtranslate_linear(bx_address laddr, unsigned pl, unsigned rw) BX_CPP_AttrRegparmN(3);
BX_SMF BX_CPP_INLINE bx_phy_address itranslate_linear(bx_address laddr, unsigned pl)
{
return translate_linear(laddr, pl, BX_READ, CODE_ACCESS);
}
BX_SMF BX_CPP_INLINE bx_phy_address dtranslate_linear(bx_address laddr, unsigned pl, unsigned rw)
{
return translate_linear(laddr, pl, rw, DATA_ACCESS);
}
BX_SMF void TLB_flush(bx_bool invalidateGlobal);
BX_SMF void TLB_invlpg(bx_address laddr);
BX_SMF void TLB_init(void);
Expand Down
18 changes: 9 additions & 9 deletions cpu/fetchdecode.cc
@@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode.cc,v 1.113 2007/10/22 17:41:41 sshwarts Exp $
// $Id: fetchdecode.cc,v 1.114 2007/11/07 10:40:40 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
Expand Down Expand Up @@ -1678,17 +1678,17 @@ BX_CPU_C::fetchDecode32(Bit8u *iptr, bxInstruction_c *instruction, unsigned rema
mod = b2 & 0xc0; // leave unshifted
nnn = (b2 >> 3) & 0x07;
rm = b2 & 0x07;
instruction->modRMForm.modRMData = (b2<<20);
instruction->modRMForm.modRMData |= mod;
instruction->modRMForm.modRMData |= (nnn<<8);
instruction->modRMForm.modRMData |= rm;
instruction->modRMForm.modRMData2 = (b2<<4);
instruction->modRMForm.modRMData1 = mod;
instruction->modRMForm.modRMData1 |= (nnn<<12);
instruction->modRMForm.modRMData1 |= rm;

// MOVs with CRx and DRx always use register ops and ignore the mod field.
if ((b1 & ~3) == 0x120)
mod = 0xc0;

if (mod == 0xc0) { // mod == 11b
instruction->metaInfo |= (1<<22); // (modC0)
instruction->assertModC0();
goto modrm_done;
}

Expand Down Expand Up @@ -1749,9 +1749,9 @@ BX_CPU_C::fetchDecode32(Bit8u *iptr, bxInstruction_c *instruction, unsigned rema
base = sib & 0x07; sib >>= 3;
index = sib & 0x07; sib >>= 3;
scale = sib;
instruction->modRMForm.modRMData |= (base<<12);
instruction->modRMForm.modRMData |= (index<<16);
instruction->modRMForm.modRMData |= (scale<<4);
instruction->modRMForm.modRMData1 |= (base<<8);
instruction->modRMForm.modRMData2 |= (index);
instruction->modRMForm.modRMData1 |= (scale<<4);
if (mod == 0x00) { // mod==00b, rm==4
instruction->ResolveModrm = BxResolve32Mod0Base[base];
if (BX_NULL_SEG_REG(instruction->seg()))
Expand Down
34 changes: 16 additions & 18 deletions cpu/fetchdecode64.cc
@@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode64.cc,v 1.118 2007/10/22 17:41:41 sshwarts Exp $
// $Id: fetchdecode64.cc,v 1.119 2007/11/07 10:40:40 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
Expand Down Expand Up @@ -2311,23 +2311,23 @@ BX_CPU_C::fetchDecode64(Bit8u *iptr, bxInstruction_c *instruction, unsigned rema
mod = b2 & 0xc0;
nnn = ((b2 >> 3) & 0x07) | rex_r;
rm = b2 & 0x07;
instruction->modRMForm.modRMData = (b2<<20);
instruction->modRMForm.modRMData |= mod;
instruction->modRMForm.modRMData |= (nnn<<8);
instruction->modRMForm.modRMData2 = (b2<<4);
instruction->modRMForm.modRMData1 = mod;
instruction->modRMForm.modRMData1 |= (nnn<<12);

// MOVs with CRx and DRx always use register ops and ignore the mod field.
if ((b1 & ~3) == 0x120)
mod = 0xc0;

if (mod == 0xc0) { // mod == 11b
rm |= rex_b;
instruction->modRMForm.modRMData |= rm;
instruction->metaInfo |= (1<<22); // (modC0)
instruction->modRMForm.modRMData1 |= rm;
instruction->assertModC0();
goto modrm_done;
}

if (rm != 4) rm |= rex_b;
instruction->modRMForm.modRMData |= rm;
instruction->modRMForm.modRMData1 |= rm;
if (instruction->as64L()) {
// 64-bit addressing modes; note that mod==11b handled above
if ((rm & 0x7) != 4) { // no s-i-b byte
Expand All @@ -2351,7 +2351,6 @@ BX_CPU_C::fetchDecode64(Bit8u *iptr, bxInstruction_c *instruction, unsigned rema
instruction->ResolveModrm = BxResolve64Mod1or2[rm];
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod01or10_rm32[rm]);
get_8bit_displ_1:
if (ilen < remain) {
// 8 sign extended to 32
instruction->modRMForm.displ32u = (Bit8s) *iptr++;
Expand All @@ -2364,7 +2363,6 @@ BX_CPU_C::fetchDecode64(Bit8u *iptr, bxInstruction_c *instruction, unsigned rema
instruction->ResolveModrm = BxResolve64Mod1or2[rm];
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod01or10_rm32[rm]);
get_32bit_displ_1:
if ((ilen+3) < remain) {
instruction->modRMForm.displ32u = FetchDWORD(iptr);
iptr += 4;
Expand All @@ -2385,29 +2383,29 @@ BX_CPU_C::fetchDecode64(Bit8u *iptr, bxInstruction_c *instruction, unsigned rema
base = (sib & 0x07) | rex_b; sib >>= 3;
index = (sib & 0x07) | rex_x; sib >>= 3;
scale = sib;
instruction->modRMForm.modRMData |= (base<<12);
instruction->modRMForm.modRMData |= (index<<16);
instruction->modRMForm.modRMData |= (scale<<4);
instruction->modRMForm.modRMData1 |= (base<<8);
instruction->modRMForm.modRMData2 |= (index);
instruction->modRMForm.modRMData1 |= (scale<<4);
if (mod == 0x00) { // mod==00b, rm==4
instruction->ResolveModrm = BxResolve64Mod0Base[base];
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod0_base32[base]);
if ((base & 0x7) == 5)
goto get_32bit_displ_1;
goto get_32bit_displ;
// mod==00b, rm==4, base!=5
goto modrm_done;
}
if (mod == 0x40) { // mod==01b, rm==4
instruction->ResolveModrm = BxResolve64Mod1or2Base[base];
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
goto get_8bit_displ_1;
goto get_8bit_displ;
}
// (mod == 0x80), mod==10b, rm==4
instruction->ResolveModrm = BxResolve64Mod1or2Base[base];
if (BX_NULL_SEG_REG(instruction->seg()))
instruction->setSeg(BX_CPU_THIS_PTR sreg_mod1or2_base32[base]);
goto get_32bit_displ_1;
goto get_32bit_displ;
}
}
else {
Expand Down Expand Up @@ -2467,9 +2465,9 @@ BX_CPU_C::fetchDecode64(Bit8u *iptr, bxInstruction_c *instruction, unsigned rema
base = (sib & 0x07) | rex_b; sib >>= 3;
index = (sib & 0x07) | rex_x; sib >>= 3;
scale = sib;
instruction->modRMForm.modRMData |= (base<<12);
instruction->modRMForm.modRMData |= (index<<16);
instruction->modRMForm.modRMData |= (scale<<4);
instruction->modRMForm.modRMData1 |= (base<<8);
instruction->modRMForm.modRMData2 |= (index);
instruction->modRMForm.modRMData1 |= (scale<<4);
if (mod == 0x00) { // mod==00b, rm==4
instruction->ResolveModrm = BxResolve32Mod0Base[base];
if (BX_NULL_SEG_REG(instruction->seg()))
Expand Down
9 changes: 2 additions & 7 deletions cpu/flag_ctrl.cc
@@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: flag_ctrl.cc,v 1.27 2007/10/21 22:07:32 sshwarts Exp $
// $Id: flag_ctrl.cc,v 1.28 2007/11/07 10:40:40 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
Expand Down Expand Up @@ -43,12 +43,7 @@ void BX_CPU_C::SAHF(bxInstruction_c *i)

void BX_CPU_C::LAHF(bxInstruction_c *i)
{
AH = (get_SF() ? 0x80 : 0) |
(get_ZF() ? 0x40 : 0) |
(get_AF() ? 0x10 : 0) |
(get_PF() ? 0x04 : 0) |
(0x02) |
(get_CF() ? 0x01 : 0);
AH = read_flags() & 0xFF;
}

void BX_CPU_C::CLC(bxInstruction_c *i)
Expand Down
14 changes: 1 addition & 13 deletions cpu/paging.cc
@@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: paging.cc,v 1.89 2007/11/01 18:03:48 sshwarts Exp $
// $Id: paging.cc,v 1.90 2007/11/07 10:40:40 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
Expand Down Expand Up @@ -1039,18 +1039,6 @@ bx_phy_address BX_CPU_C::translate_linear(bx_address laddr, unsigned pl, unsigne
return paddress;
}

bx_phy_address BX_CPP_AttrRegparmN(3)
BX_CPU_C::dtranslate_linear(bx_address laddr, unsigned pl, unsigned rw)
{
return translate_linear(laddr, pl, rw, DATA_ACCESS);
}

bx_phy_address BX_CPP_AttrRegparmN(2)
BX_CPU_C::itranslate_linear(bx_address laddr, unsigned pl)
{
return translate_linear(laddr, pl, BX_READ, CODE_ACCESS);
}

#if BX_DEBUGGER || BX_DISASM || BX_INSTRUMENTATION || BX_GDBSTUB

bx_bool BX_CPU_C::dbg_xlate_linear2phy(bx_address laddr, bx_phy_address *phy)
Expand Down

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