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[ath5k] Save proper cacheline size when fixing PCI configuration
Some BIOSes set the PCI cacheline size to zero for the card; the ath5k driver fixes it to a reasonable in PCI config space, but failed to correct the internal value it had already read. This resulted in divide-by-zero errors when cacheline-aligning various data structures. Fix by setting the internal cachelsz to a sane value at the same time as we write that value to PCI config space. Signed-off-by: Marty Connor <mdc@etherboot.org>
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